On 8/26/2026 7:05 PM, Joel Stanley wrote:
The CPS device maps some devices into a container region, but the
ACLINT and APLIC were mapped directly to system_memory.
Pass the container memory region to the interrupt controller helpers so
all CPS devices live in the container. The location of devices in memory
for the boston-aia machine is unchanged.
Signed-off-by: Joel Stanley <[email protected]>
---
Reviewed-by: Daniel Henrique Barboza <[email protected]>
hw/riscv/cps.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/cps.c b/hw/riscv/cps.c
index d2fd9638a08d..21daaf4943d8 100644
--- a/hw/riscv/cps.c
+++ b/hw/riscv/cps.c
@@ -135,7 +135,7 @@ static void riscv_cps_realize(DeviceState *dev, Error
**errp)
for (i = 0; i < num_of_clusters; i++) {
uint64_t cm_base = GLOBAL_CM_BASE + (CM_SIZE * i);
uint32_t hartid_base = i << MHARTID_CLUSTER_SHIFT;
- s->aplic = riscv_aplic_create(get_system_memory(),
+ s->aplic = riscv_aplic_create(&s->container,
cm_base + AIA_PLIC_M_OFFSET,
AIA_PLIC_M_SIZE,
hartid_base, /* hartid_base */
@@ -143,7 +143,7 @@ static void riscv_cps_realize(DeviceState *dev, Error
**errp)
APLIC_NUM_SOURCES,
APLIC_NUM_PRIO_BITS,
false, true, NULL);
- riscv_aplic_create(get_system_memory(),
+ riscv_aplic_create(&s->container,
cm_base + AIA_PLIC_S_OFFSET,
AIA_PLIC_S_SIZE,
hartid_base, /* hartid_base */
@@ -153,10 +153,10 @@ static void riscv_cps_realize(DeviceState *dev, Error
**errp)
false, false, s->aplic);
/* PLIC changes msi_nonbroken to ture. We revert the change. */
msi_nonbroken = false;
- riscv_aclint_swi_create(get_system_memory(),
+ riscv_aclint_swi_create(&s->container,
cm_base + AIA_CLINT_OFFSET,
hartid_base, MAX_HARTS, false);
- riscv_aclint_mtimer_create(get_system_memory(),
+ riscv_aclint_mtimer_create(&s->container,
cm_base + AIA_CLINT_OFFSET +
RISCV_ACLINT_SWI_SIZE,
RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
