Remove the direct use of MachineState from the device tree creation to allow separation between the SoC (TTAtlantisState) and the QEMU MachineState.
Fix this for the device tree pointer by passing it directly to the functions that use it, instead of casting the TTAtlantisState to a MachineState. MachineState::smp.cpus is replaced with TTAtlantisState::cpus.num_harts, as these are equivalent after tt_atlantis_machine_init. Signed-off-by: Joel Stanley <[email protected]> --- hw/riscv/tt_atlantis.c | 51 +++++++++++++++++++----------------------- 1 file changed, 23 insertions(+), 28 deletions(-) diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 35b3be072a06..c471c7cebf12 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -80,9 +80,8 @@ static uint32_t next_phandle(void) return fdt_phandle++; } -static void create_fdt_memory(TTAtlantisState *s) +static void create_fdt_memory(void *fdt, TTAtlantisState *s) { - void *fdt = MACHINE(s)->fdt; hwaddr size_lo = MACHINE(s)->ram_size; hwaddr size_hi = 0; @@ -104,9 +103,9 @@ static void create_fdt_memory(TTAtlantisState *s) } } -static void create_fdt_aclint(TTAtlantisState *s, uint32_t *intc_phandles) +static void create_fdt_aclint(void *fdt, TTAtlantisState *s, + uint32_t *intc_phandles) { - void *fdt = MACHINE(s)->fdt; g_autofree char *name = NULL; g_autofree uint32_t *aclint_mtimer_cells = NULL; uint32_t aclint_cells_size; @@ -206,10 +205,9 @@ static void create_fdt_one_aplic(void *fdt, qemu_fdt_setprop_cell(fdt, name, "phandle", aplic_phandle); } -static void create_fdt_pmu(TTAtlantisState *s) +static void create_fdt_pmu(void *fdt, TTAtlantisState *s) { char pmu_name[] = "/pmu"; - void *fdt = MACHINE(s)->fdt; RISCVCPU *hart = &s->cpus.harts[0]; qemu_fdt_add_subnode(fdt, pmu_name); @@ -217,32 +215,29 @@ static void create_fdt_pmu(TTAtlantisState *s) riscv_pmu_generate_fdt_node(fdt, hart->pmu_avail_ctrs, pmu_name); } -static void create_fdt_cpu(TTAtlantisState *s, const MemMapEntry *memmap, +static void create_fdt_cpu(void *fdt, TTAtlantisState *s, uint32_t aplic_s_phandle, uint32_t imsic_s_phandle) { - MachineState *ms = MACHINE(s); - void *fdt = MACHINE(s)->fdt; - g_autofree uint32_t *intc_phandles = g_new0(uint32_t, ms->smp.cpus); + g_autofree uint32_t *intc_phandles = g_new0(uint32_t, s->cpus.num_harts); + int num_harts = s->cpus.num_harts; fdt_create_cpu_socket_subnode(fdt, TT_ACLINT_TIMEBASE_FREQ); - create_fdt_socket_cpus(fdt, s->cpus.harts, 0, s->cpus.num_harts, + create_fdt_socket_cpus(fdt, s->cpus.harts, 0, num_harts, s->cpus.hartid_base, &fdt_phandle, intc_phandles, false, false); - create_fdt_memory(s); - - create_fdt_aclint(s, intc_phandles); + create_fdt_aclint(fdt, s, intc_phandles); /* M-level IMSIC node */ uint32_t msi_m_phandle = next_phandle(); - create_fdt_one_imsic(fdt, &s->memmap[TT_ATL_MIMSIC], ms->smp.cpus, + create_fdt_one_imsic(fdt, &s->memmap[TT_ATL_MIMSIC], num_harts, intc_phandles, msi_m_phandle, IRQ_M_EXT, TT_IMSIC_GUEST_BITS); /* S-level IMSIC node */ - create_fdt_one_imsic(fdt, &s->memmap[TT_ATL_SIMSIC], ms->smp.cpus, + create_fdt_one_imsic(fdt, &s->memmap[TT_ATL_SIMSIC], num_harts, intc_phandles, imsic_s_phandle, IRQ_S_EXT, TT_IMSIC_GUEST_BITS); @@ -252,13 +247,13 @@ static void create_fdt_cpu(TTAtlantisState *s, const MemMapEntry *memmap, create_fdt_one_aplic(fdt, &s->memmap[TT_ATL_MAPLIC], msi_m_phandle, intc_phandles, aplic_m_phandle, aplic_s_phandle, - IRQ_M_EXT, s->cpus.num_harts); + IRQ_M_EXT, num_harts); /* S-level APLIC node */ create_fdt_one_aplic(fdt, &s->memmap[TT_ATL_SAPLIC], imsic_s_phandle, intc_phandles, aplic_s_phandle, 0, - IRQ_S_EXT, s->cpus.num_harts); + IRQ_S_EXT, num_harts); } static void create_fdt_uart(void *fdt, const MemMapEntry *mem, int irq, @@ -317,10 +312,9 @@ static void create_fdt_i2c(void *fdt, const MemMapEntry *mem, uint32_t irq, qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0); } -static void create_fdt_i2c_device(TTAtlantisState *s, int bus, +static void create_fdt_i2c_device(void *fdt, TTAtlantisState *s, int bus, const char *compat, int addr) { - void *fdt = MACHINE(s)->fdt; hwaddr base = s->memmap[TT_ATL_I2C0 + bus].base; g_autofree char *name = g_strdup_printf("/soc/i2c@%"HWADDR_PRIX"/sensor@%x", base, addr); @@ -330,14 +324,15 @@ static void create_fdt_i2c_device(TTAtlantisState *s, int bus, qemu_fdt_setprop_cell(fdt, name, "reg", addr); } -static void finalize_fdt(TTAtlantisState *s) +static void finalize_fdt(void *fdt, TTAtlantisState *s) { uint32_t aplic_s_phandle = next_phandle(); uint32_t imsic_s_phandle = next_phandle(); uint32_t periph_clk_phandle = next_phandle(); - void *fdt = MACHINE(s)->fdt; - create_fdt_cpu(s, s->memmap, aplic_s_phandle, imsic_s_phandle); + create_fdt_cpu(fdt, s, aplic_s_phandle, imsic_s_phandle); + + create_fdt_memory(fdt, s); /* * We want to do this, but the Linux aplic driver was broken before v6.16 @@ -359,8 +354,8 @@ static void finalize_fdt(TTAtlantisState *s) } /* I2C peripherals: qemu specific */ - create_fdt_i2c_device(s, 0, "dallas,ds1338", 0x6f); - create_fdt_i2c_device(s, 4, "ti,tmp105", 0x48); + create_fdt_i2c_device(fdt, s, 0, "dallas,ds1338", 0x6f); + create_fdt_i2c_device(fdt, s, 4, "ti,tmp105", 0x48); } static void create_fdt(TTAtlantisState *s) @@ -377,7 +372,7 @@ static void create_fdt(TTAtlantisState *s) qemu_fdt_add_subnode(ms->fdt, "/aliases"); - create_fdt_pmu(s); + create_fdt_pmu(ms->fdt, s); } static void load_fdt(TTAtlantisState *s) @@ -408,7 +403,7 @@ static void load_fdt(TTAtlantisState *s) g_strfreev(node_path); } - create_fdt_memory(s); + create_fdt_memory(ms->fdt, s); } static void mmio_map_unimplemented(MemoryRegion *memory, SysBusDevice *dev, @@ -439,7 +434,7 @@ static void tt_atlantis_machine_done(Notifier *notifier, void *data) * dynamic sysbus devices. Our FDT needs to be finalized. */ if (machine->dtb == NULL) { - finalize_fdt(s); + finalize_fdt(machine->fdt, s); } mem_size = machine->ram_size; -- 2.47.3
