On 8/26/2026 7:11 PM, Joel Stanley wrote:
From: Portia Stephens <[email protected]>
There are platforms where CPUs have different mapping of system memory.
The global system memory does not allow for this. This adds an optional
property to assign a specific memory region to a hart. This allows for a
machine to alias the hart's memory to system memory while the hart only
views memory from its own memory region.
LGTM but please clarify in the commit msg that the memory region is being
assigned to the hart array, not "to a hart". A hart is a single hardware
thread.
E.g.:
"(...) This adds an optional property to assign a specific memory region to the
hart array. This allows for a machine to alias the array's memory to
system memory while the array only views memory from its own memory region."
With the commit msg change:
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Signed-off-by: Portia Stephens <[email protected]>
Signed-off-by: Joel Stanley <[email protected]>
---
include/hw/riscv/riscv_hart.h | 2 ++
hw/riscv/riscv_hart.c | 8 ++++++++
2 files changed, 10 insertions(+)
diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h
index 197fa1623115..c3cd05a2c877 100644
--- a/include/hw/riscv/riscv_hart.h
+++ b/include/hw/riscv/riscv_hart.h
@@ -42,6 +42,8 @@ struct RISCVHartArrayState {
uint64_t *rnmi_irqvec;
uint32_t num_rnmi_excpvec;
uint64_t *rnmi_excpvec;
+ /* Optional private memory region for use instead of system memory */
+ MemoryRegion *memory;
RISCVCPU *harts;
};
diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
index 747754be6158..32fd39737ff6 100644
--- a/hw/riscv/riscv_hart.c
+++ b/hw/riscv/riscv_hart.c
@@ -53,6 +53,8 @@ static const Property riscv_harts_props[] = {
DEFINE_PROP_ARRAY("rnmi-exception-vector", RISCVHartArrayState,
num_rnmi_excpvec, rnmi_excpvec, qdev_prop_uint64,
uint64_t),
+ DEFINE_PROP_LINK("memory", RISCVHartArrayState, memory,
+ TYPE_MEMORY_REGION, MemoryRegion *),
};
static void riscv_harts_cpu_reset(void *opaque)
@@ -117,6 +119,12 @@ static bool riscv_hart_realize(RISCVHartArrayState *s, int
idx,
object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_type);
qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec);
+ /* Use private memory instead of system_memory if provided */
+ if (s->memory) {
+ object_property_set_link(OBJECT(&s->harts[idx]), "memory",
+ OBJECT(s->memory), &error_abort);
+ }
+
if (s->harts[idx].cfg.ext_smrnmi) {
if (idx < s->num_rnmi_irqvec) {
qdev_prop_set_uint64(DEVICE(&s->harts[idx]),
