The draft Zvabd extension provides vector integer absolute-difference
operations for image, video, and other data-processing workloads. It
introduces eight new instructions:
- vabd.vv, vabd.vx, vabdu.vv, and vabdu.vx support SEW values from
8 through ELEN, with SEW 64 requiring Zve64x.
- vwabda.vv, vwabda.vx, vwabdau.vv, and vwabdau.vx support SEW 8
and 16 and accumulate into a double-width destination.
The specification is under review at:
https://github.com/riscv/riscv-isa-manual/pull/3279
These patch implement this instruction extension, including instruction
decoder, TCG translation, helpers, and tests, etc.
After the first review, this patch has been updated as follows:
- Added support for recognizing the vabs.v pseudo-instruction in the
disassembler.
- Added tests for the eight Zvabd instructions based on Daniel's tests.
Mingliang Liu (2):
disas/riscv: Support vabs.v pseudo-instruction
tests/tcg/riscv64: Add tests for Zvabd extension
Zhibo Hong (1):
target/riscv: Add experimental Zvabd extension support
disas/riscv-op.c.inc | 9 +
disas/riscv.c | 14 +
target/riscv/cpu.c | 1 +
target/riscv/cpu_cfg_fields.h.inc | 1 +
target/riscv/helper.h | 26 +
target/riscv/insn32.decode | 10 +
target/riscv/tcg/insn_trans/trans_rvv.c.inc | 45 ++
target/riscv/tcg/tcg-cpu.c | 6 +
target/riscv/tcg/vector_helper.c | 56 ++
tests/tcg/riscv64/Makefile.softmmu-target | 8 +
tests/tcg/riscv64/test-zvabd.S | 659 ++++++++++++++++++++
11 files changed, 835 insertions(+)
create mode 100644 tests/tcg/riscv64/test-zvabd.S
--
2.39.5
