On Mon, 31 Aug 2026 at 22:59, Mingliang Liu <[email protected]> wrote: > > From: Zhibo Hong <[email protected]> > > The draft Zvabd extension provides vector integer absolute-difference > operations for image, video, and other data-processing workloads. It > introduces eight new instructions: > > - vabd.vv, vabd.vx, vabdu.vv, and vabdu.vx support SEW values from > 8 through ELEN, with SEW 64 requiring Zve64x. > - vwabda.vv, vwabda.vx, vwabdau.vv, and vwabdau.vx support SEW 8 > and 16 and accumulate into a double-width destination. > > This patch implement this instruction extension, including instruction > decoder, TCG translation, and helpers, etc. > > The specification is under review at: > https://github.com/riscv/riscv-isa-manual/pull/3279
Mention this implements 0.9 of the spec. It's notable that the opcodes (and other things) have changed since 0.7. > Signed-off-by: Mingliang Liu <[email protected]> Assuming we follow the same convention as the kernel, include a Signed-off-by line from the author, followed by yours as the submitter. > --- a/disas/riscv.c > +++ b/disas/riscv.c > @@ -2417,6 +2423,8 @@ static const rv_opcode_data > *decode_inst_opcode(rv_decode *dec, rv_isa isa) > case 13: return &op_vclmulh_vx; > case 14: return &op_vslide1up_vx; > case 15: return &op_vslide1down_vx; > + case 21: return &op_vabd_vx; > + case 22: return &op_vabdu_vx; Should these be in numerical order? Otherwise, looks good. Reviewed-by: Joel Stanley <[email protected]> > case 16: > switch ((inst >> 20) & 0b11111) { > case 0:
