Model GPIO control registers and the PROC0, PROC1 and dormant-wake interrupt banks, including atomic aliases and last-bank masks. Connect the PROC0 interrupt output to the Cortex-M0+ NVIC and add focused qtests for register behavior and interrupt propagation.
Signed-off-by: gilles grimaud <[email protected]> --- hw/arm/rp2040.c | 11 +- hw/misc/meson.build | 1 + hw/misc/rp2040_iobank0.c | 333 ++++++++++++++++++++++++++++++ include/hw/arm/rp2040.h | 2 + include/hw/misc/rp2040_iobank0.h | 45 ++++ tests/qtest/meson.build | 1 + tests/qtest/rp2040-iobank0-test.c | 119 +++++++++++ 7 files changed, 511 insertions(+), 1 deletion(-) create mode 100644 hw/misc/rp2040_iobank0.c create mode 100644 include/hw/misc/rp2040_iobank0.h create mode 100644 tests/qtest/rp2040-iobank0-test.c diff --git a/hw/arm/rp2040.c b/hw/arm/rp2040.c index 15a5cb0d3f..a52738b3e2 100644 --- a/hw/arm/rp2040.c +++ b/hw/arm/rp2040.c @@ -22,6 +22,7 @@ #define RP2040_UART0_IRQ 20 #define RP2040_UART1_BASE 0x40038000 #define RP2040_UART1_IRQ 21 +#define RP2040_IO_IRQ_BANK0 13 /* * Temporary boot ROM used until the synthetic ROM is introduced. It loads @@ -48,7 +49,6 @@ static const struct { hwaddr base; hwaddr size; } rp2040_unimplemented[] = { - { "rp2040.iobank0", 0x40014000, 0x4000 }, { "rp2040.ioqspi", 0x40018000, 0x4000 }, { "rp2040.busctrl", 0x40030000, 0x4000 }, { "rp2040.uart0_aliases", 0x40035000, 0x3000 }, @@ -130,6 +130,8 @@ static void rp2040_soc_init(Object *obj) } object_initialize_child(obj, "clocks", &s->clocks, TYPE_RP2040_CLOCKS); + object_initialize_child(obj, "iobank0", &s->iobank0, + TYPE_RP2040_IOBANK0); object_initialize_child(obj, "pads-bank0", &s->pads_bank0, TYPE_RP2040_PADS_BANK0); object_initialize_child(obj, "pads-qspi", &s->pads_qspi, @@ -320,6 +322,13 @@ static void rp2040_soc_realize(DeviceState *dev, Error **errp) } sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysinfo), 0, RP2040_SYSINFO_BASE); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->iobank0), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->iobank0), 0, RP2040_IOBANK0_BASE); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->iobank0), 0, + s->irq[RP2040_IO_IRQ_BANK0]); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->rosc), errp)) { return; } diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 0c5f8f2b4a..18a0afdc93 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -99,6 +99,7 @@ system_ss.add(when: 'CONFIG_RASPI', if_true: files( 'bcm2835_powermgt.c', )) system_ss.add(when: 'CONFIG_RP2040', if_true: files('rp2040_clocks.c')) +system_ss.add(when: 'CONFIG_RP2040', if_true: files('rp2040_iobank0.c')) system_ss.add(when: 'CONFIG_RP2040', if_true: files('rp2040_pads.c')) system_ss.add(when: 'CONFIG_RP2040', if_true: files('rp2040_pll.c')) system_ss.add(when: 'CONFIG_RP2040', if_true: files('rp2040_psm.c')) diff --git a/hw/misc/rp2040_iobank0.c b/hw/misc/rp2040_iobank0.c new file mode 100644 index 0000000000..3ecb30b60f --- /dev/null +++ b/hw/misc/rp2040_iobank0.c @@ -0,0 +1,333 @@ +/* + * RP2040 GPIO IO bank emulation + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/misc/rp2040_iobank0.h" +#include "hw/misc/rp2040.h" +#include "hw/core/irq.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "qemu/module.h" + +#define IOBANK0_GPIO_STRIDE 0x8 +#define IOBANK0_GPIO_STATUS 0x0 +#define IOBANK0_GPIO_CTRL 0x4 + +#define IOBANK0_INTR 0x0f0 +#define IOBANK0_PROC0_INTE 0x100 +#define IOBANK0_PROC0_INTF 0x110 +#define IOBANK0_PROC0_INTS 0x120 +#define IOBANK0_PROC1_INTE 0x130 +#define IOBANK0_PROC1_INTF 0x140 +#define IOBANK0_PROC1_INTS 0x150 +#define IOBANK0_DORMANT_INTE 0x160 +#define IOBANK0_DORMANT_INTF 0x170 +#define IOBANK0_DORMANT_INTS 0x180 + +#define IOBANK0_CTRL_RESET 0x1f +#define IOBANK0_CTRL_RW_MASK 0x33333f +#define IOBANK0_CTRL_FUNCSEL_MASK 0x1f +#define IOBANK0_FUNCSEL_UART 2 +#define IOBANK0_INTR_EDGE_MASK 0xcccccccc +#define IOBANK0_INTR_LAST_EDGE_MASK 0x00cccccc +#define IOBANK0_IRQ_MASK 0xffffffff +#define IOBANK0_IRQ_LAST_MASK 0x00ffffff + +static bool rp2040_iobank0_gpio_offset(hwaddr offset, unsigned *gpio, + unsigned *reg) +{ + if (offset >= RP2040_IOBANK0_NUM_GPIOS * IOBANK0_GPIO_STRIDE) { + return false; + } + + *gpio = offset / IOBANK0_GPIO_STRIDE; + *reg = offset & (IOBANK0_GPIO_STRIDE - 1); + return *reg == IOBANK0_GPIO_STATUS || *reg == IOBANK0_GPIO_CTRL; +} + +static bool rp2040_iobank0_bank_offset(hwaddr offset, hwaddr base, + unsigned *bank) +{ + if (offset < base || offset >= base + RP2040_IOBANK0_IRQ_BANKS * 4 || + (offset & 0x3)) { + return false; + } + + *bank = (offset - base) / 4; + return true; +} + +static uint32_t rp2040_iobank0_irq_mask(unsigned bank) +{ + return bank == 3 ? IOBANK0_IRQ_LAST_MASK : IOBANK0_IRQ_MASK; +} + +static uint32_t rp2040_iobank0_intr_edge_mask(unsigned bank) +{ + return bank == 3 ? IOBANK0_INTR_LAST_EDGE_MASK : IOBANK0_INTR_EDGE_MASK; +} + +static uint32_t rp2040_iobank0_ints(uint32_t intr, uint32_t inte, + uint32_t intf) +{ + return (intr & inte) | intf; +} + +static bool rp2040_iobank0_gpio_is_uart(RP2040IoBank0State *s, unsigned gpio) +{ + return (s->ctrl[gpio] & IOBANK0_CTRL_FUNCSEL_MASK) == IOBANK0_FUNCSEL_UART; +} + +bool rp2040_iobank0_uart0_tx_enabled(RP2040IoBank0State *s) +{ + return rp2040_iobank0_gpio_is_uart(s, 0); +} + +bool rp2040_iobank0_uart0_rx_enabled(RP2040IoBank0State *s) +{ + return rp2040_iobank0_gpio_is_uart(s, 1); +} + +bool rp2040_iobank0_uart1_tx_enabled(RP2040IoBank0State *s) +{ + return rp2040_iobank0_gpio_is_uart(s, 4); +} + +bool rp2040_iobank0_uart1_rx_enabled(RP2040IoBank0State *s) +{ + return rp2040_iobank0_gpio_is_uart(s, 5); +} + +static void rp2040_iobank0_update_uart_pins(RP2040IoBank0State *s) +{ + qemu_set_irq(s->uart0_pin[0], rp2040_iobank0_uart0_tx_enabled(s)); + qemu_set_irq(s->uart0_pin[1], rp2040_iobank0_uart0_rx_enabled(s)); + qemu_set_irq(s->uart1_pin[0], rp2040_iobank0_uart1_tx_enabled(s)); + qemu_set_irq(s->uart1_pin[1], rp2040_iobank0_uart1_rx_enabled(s)); +} + +static void rp2040_iobank0_update_irq(RP2040IoBank0State *s) +{ + bool proc0_level = false; + bool proc1_level = false; + int i; + + for (i = 0; i < RP2040_IOBANK0_IRQ_BANKS; i++) { + proc0_level |= rp2040_iobank0_ints(s->intr[i], s->proc0_inte[i], + s->proc0_intf[i]) != 0; + proc1_level |= rp2040_iobank0_ints(s->intr[i], s->proc1_inte[i], + s->proc1_intf[i]) != 0; + } + + qemu_set_irq(s->proc0_irq, proc0_level); + qemu_set_irq(s->proc1_irq, proc1_level); +} + +static uint64_t rp2040_iobank0_read(void *opaque, hwaddr addr, unsigned size) +{ + RP2040IoBank0State *s = opaque; + hwaddr offset = addr & 0xfff; + unsigned gpio; + unsigned reg; + unsigned bank; + uint64_t value; + + if (rp2040_iobank0_gpio_offset(offset, &gpio, ®)) { + value = reg == IOBANK0_GPIO_STATUS ? 0 : s->ctrl[gpio]; + } else if (rp2040_iobank0_bank_offset(offset, IOBANK0_INTR, &bank)) { + value = s->intr[bank]; + } else if (rp2040_iobank0_bank_offset(offset, IOBANK0_PROC0_INTE, &bank)) { + value = s->proc0_inte[bank]; + } else if (rp2040_iobank0_bank_offset(offset, IOBANK0_PROC0_INTF, &bank)) { + value = s->proc0_intf[bank]; + } else if (rp2040_iobank0_bank_offset(offset, IOBANK0_PROC0_INTS, &bank)) { + value = rp2040_iobank0_ints(s->intr[bank], s->proc0_inte[bank], + s->proc0_intf[bank]); + } else if (rp2040_iobank0_bank_offset(offset, IOBANK0_PROC1_INTE, &bank)) { + value = s->proc1_inte[bank]; + } else if (rp2040_iobank0_bank_offset(offset, IOBANK0_PROC1_INTF, &bank)) { + value = s->proc1_intf[bank]; + } else if (rp2040_iobank0_bank_offset(offset, IOBANK0_PROC1_INTS, &bank)) { + value = rp2040_iobank0_ints(s->intr[bank], s->proc1_inte[bank], + s->proc1_intf[bank]); + } else if (rp2040_iobank0_bank_offset(offset, IOBANK0_DORMANT_INTE, + &bank)) { + value = s->dormant_wake_inte[bank]; + } else if (rp2040_iobank0_bank_offset(offset, IOBANK0_DORMANT_INTF, + &bank)) { + value = s->dormant_wake_intf[bank]; + } else if (rp2040_iobank0_bank_offset(offset, IOBANK0_DORMANT_INTS, + &bank)) { + value = rp2040_iobank0_ints(s->intr[bank], + s->dormant_wake_inte[bank], + s->dormant_wake_intf[bank]); + } else { + value = 0; + qemu_log_mask(LOG_UNIMP, + "%s: unimplemented read at offset 0x%" + HWADDR_PRIx "\n", __func__, addr & 0xfff); + } + + return value; +} + +static void rp2040_iobank0_write_irq_reg(uint32_t *reg, uint64_t value64, + hwaddr alias, unsigned bank) +{ + *reg = rp2040_atomic_update(*reg, value64, alias) & + rp2040_iobank0_irq_mask(bank); +} + +static void rp2040_iobank0_write(void *opaque, hwaddr addr, uint64_t value64, + unsigned size) +{ + RP2040IoBank0State *s = opaque; + hwaddr alias = addr & RP2040_ATOMIC_ALIAS_MASK; + hwaddr offset = addr & 0xfff; + unsigned gpio; + unsigned reg; + unsigned bank; + uint32_t value = value64; + + if (rp2040_iobank0_gpio_offset(offset, &gpio, ®)) { + if (reg == IOBANK0_GPIO_CTRL) { + s->ctrl[gpio] = + rp2040_atomic_update(s->ctrl[gpio], value, alias) & + IOBANK0_CTRL_RW_MASK; + if (gpio <= 1 || gpio == 4 || gpio == 5) { + rp2040_iobank0_update_uart_pins(s); + } + } + } else if (rp2040_iobank0_bank_offset(offset, IOBANK0_INTR, &bank)) { + s->intr[bank] &= ~(value & rp2040_iobank0_intr_edge_mask(bank)); + rp2040_iobank0_update_irq(s); + } else if (rp2040_iobank0_bank_offset(offset, IOBANK0_PROC0_INTE, &bank)) { + rp2040_iobank0_write_irq_reg(&s->proc0_inte[bank], value, alias, + bank); + rp2040_iobank0_update_irq(s); + } else if (rp2040_iobank0_bank_offset(offset, IOBANK0_PROC0_INTF, &bank)) { + rp2040_iobank0_write_irq_reg(&s->proc0_intf[bank], value, alias, + bank); + rp2040_iobank0_update_irq(s); + } else if (rp2040_iobank0_bank_offset(offset, IOBANK0_PROC1_INTE, &bank)) { + rp2040_iobank0_write_irq_reg(&s->proc1_inte[bank], value, alias, + bank); + rp2040_iobank0_update_irq(s); + } else if (rp2040_iobank0_bank_offset(offset, IOBANK0_PROC1_INTF, &bank)) { + rp2040_iobank0_write_irq_reg(&s->proc1_intf[bank], value, alias, + bank); + rp2040_iobank0_update_irq(s); + } else if (rp2040_iobank0_bank_offset(offset, IOBANK0_DORMANT_INTE, + &bank)) { + rp2040_iobank0_write_irq_reg(&s->dormant_wake_inte[bank], value, + alias, bank); + } else if (rp2040_iobank0_bank_offset(offset, IOBANK0_DORMANT_INTF, + &bank)) { + rp2040_iobank0_write_irq_reg(&s->dormant_wake_intf[bank], value, + alias, bank); + } else if (!rp2040_iobank0_bank_offset(offset, IOBANK0_PROC0_INTS, + &bank) && + !rp2040_iobank0_bank_offset(offset, IOBANK0_PROC1_INTS, + &bank) && + !rp2040_iobank0_bank_offset(offset, IOBANK0_DORMANT_INTS, + &bank)) { + qemu_log_mask(LOG_UNIMP, + "%s: unimplemented write at offset 0x%" + HWADDR_PRIx "\n", __func__, addr & 0xfff); + } +} + +static const MemoryRegionOps rp2040_iobank0_ops = { + .read = rp2040_iobank0_read, + .write = rp2040_iobank0_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, +}; + +static void rp2040_iobank0_reset(DeviceState *dev) +{ + RP2040IoBank0State *s = RP2040_IOBANK0(dev); + int i; + + for (i = 0; i < ARRAY_SIZE(s->ctrl); i++) { + s->ctrl[i] = IOBANK0_CTRL_RESET; + } + + memset(s->intr, 0, sizeof(s->intr)); + memset(s->proc0_inte, 0, sizeof(s->proc0_inte)); + memset(s->proc0_intf, 0, sizeof(s->proc0_intf)); + memset(s->proc1_inte, 0, sizeof(s->proc1_inte)); + memset(s->proc1_intf, 0, sizeof(s->proc1_intf)); + memset(s->dormant_wake_inte, 0, sizeof(s->dormant_wake_inte)); + memset(s->dormant_wake_intf, 0, sizeof(s->dormant_wake_intf)); + rp2040_iobank0_update_irq(s); + rp2040_iobank0_update_uart_pins(s); +} + +static void rp2040_iobank0_init(Object *obj) +{ + RP2040IoBank0State *s = RP2040_IOBANK0(obj); + + memory_region_init_io(&s->iomem, obj, &rp2040_iobank0_ops, s, + "rp2040.iobank0", RP2040_IOBANK0_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->proc0_irq); + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->proc1_irq); + qdev_init_gpio_out_named(DEVICE(obj), s->uart0_pin, "uart0-pin", + ARRAY_SIZE(s->uart0_pin)); + qdev_init_gpio_out_named(DEVICE(obj), s->uart1_pin, "uart1-pin", + ARRAY_SIZE(s->uart1_pin)); +} + +static const VMStateDescription rp2040_iobank0_vmstate = { + .name = TYPE_RP2040_IOBANK0, + .version_id = 1, + .minimum_version_id = 1, + .fields = (const VMStateField[]) { + VMSTATE_UINT32_ARRAY(ctrl, RP2040IoBank0State, + RP2040_IOBANK0_NUM_GPIOS), + VMSTATE_UINT32_ARRAY(intr, RP2040IoBank0State, + RP2040_IOBANK0_IRQ_BANKS), + VMSTATE_UINT32_ARRAY(proc0_inte, RP2040IoBank0State, + RP2040_IOBANK0_IRQ_BANKS), + VMSTATE_UINT32_ARRAY(proc0_intf, RP2040IoBank0State, + RP2040_IOBANK0_IRQ_BANKS), + VMSTATE_UINT32_ARRAY(proc1_inte, RP2040IoBank0State, + RP2040_IOBANK0_IRQ_BANKS), + VMSTATE_UINT32_ARRAY(proc1_intf, RP2040IoBank0State, + RP2040_IOBANK0_IRQ_BANKS), + VMSTATE_UINT32_ARRAY(dormant_wake_inte, RP2040IoBank0State, + RP2040_IOBANK0_IRQ_BANKS), + VMSTATE_UINT32_ARRAY(dormant_wake_intf, RP2040IoBank0State, + RP2040_IOBANK0_IRQ_BANKS), + VMSTATE_END_OF_LIST() + } +}; + +static void rp2040_iobank0_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + device_class_set_legacy_reset(dc, rp2040_iobank0_reset); + dc->vmsd = &rp2040_iobank0_vmstate; +} + +static const TypeInfo rp2040_iobank0_info = { + .name = TYPE_RP2040_IOBANK0, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(RP2040IoBank0State), + .instance_init = rp2040_iobank0_init, + .class_init = rp2040_iobank0_class_init, +}; + +static void rp2040_iobank0_register_types(void) +{ + type_register_static(&rp2040_iobank0_info); +} +type_init(rp2040_iobank0_register_types) diff --git a/include/hw/arm/rp2040.h b/include/hw/arm/rp2040.h index 42eb3c8fca..ae393195d3 100644 --- a/include/hw/arm/rp2040.h +++ b/include/hw/arm/rp2040.h @@ -14,6 +14,7 @@ #include "hw/core/clock.h" #include "hw/core/sysbus.h" #include "hw/misc/rp2040_clocks.h" +#include "hw/misc/rp2040_iobank0.h" #include "hw/misc/rp2040_pads.h" #include "hw/misc/rp2040_pll.h" #include "hw/misc/rp2040_psm.h" @@ -48,6 +49,7 @@ struct RP2040State { ARMv7MState armv7m[RP2040_NUM_CORES]; PL011State uart[2]; RP2040ClocksState clocks; + RP2040IoBank0State iobank0; RP2040PadsBank0State pads_bank0; RP2040PadsQspiState pads_qspi; RP2040PllState pll_sys; diff --git a/include/hw/misc/rp2040_iobank0.h b/include/hw/misc/rp2040_iobank0.h new file mode 100644 index 0000000000..93f5b4b2f4 --- /dev/null +++ b/include/hw/misc/rp2040_iobank0.h @@ -0,0 +1,45 @@ +/* + * RP2040 GPIO IO bank emulation + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_MISC_RP2040_IOBANK0_H +#define HW_MISC_RP2040_IOBANK0_H + +#include "hw/core/sysbus.h" +#include "qom/object.h" + +#define TYPE_RP2040_IOBANK0 "rp2040-iobank0" +OBJECT_DECLARE_SIMPLE_TYPE(RP2040IoBank0State, RP2040_IOBANK0) + +#define RP2040_IOBANK0_BASE 0x40014000 +#define RP2040_IOBANK0_SIZE 0x4000 +#define RP2040_IOBANK0_NUM_GPIOS 30 +#define RP2040_IOBANK0_IRQ_BANKS 4 + +struct RP2040IoBank0State { + SysBusDevice parent_obj; + + MemoryRegion iomem; + qemu_irq proc0_irq; + qemu_irq proc1_irq; + qemu_irq uart0_pin[2]; + qemu_irq uart1_pin[2]; + + uint32_t ctrl[RP2040_IOBANK0_NUM_GPIOS]; + uint32_t intr[RP2040_IOBANK0_IRQ_BANKS]; + uint32_t proc0_inte[RP2040_IOBANK0_IRQ_BANKS]; + uint32_t proc0_intf[RP2040_IOBANK0_IRQ_BANKS]; + uint32_t proc1_inte[RP2040_IOBANK0_IRQ_BANKS]; + uint32_t proc1_intf[RP2040_IOBANK0_IRQ_BANKS]; + uint32_t dormant_wake_inte[RP2040_IOBANK0_IRQ_BANKS]; + uint32_t dormant_wake_intf[RP2040_IOBANK0_IRQ_BANKS]; +}; + +bool rp2040_iobank0_uart0_tx_enabled(RP2040IoBank0State *s); +bool rp2040_iobank0_uart0_rx_enabled(RP2040IoBank0State *s); +bool rp2040_iobank0_uart1_tx_enabled(RP2040IoBank0State *s); +bool rp2040_iobank0_uart1_rx_enabled(RP2040IoBank0State *s); + +#endif diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 26ed04bc51..9cf40e50ec 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -266,6 +266,7 @@ qtests_arm = \ ['rp2040-syscfg-test', 'rp2040-sysinfo-test', 'rp2040-clocks-test', + 'rp2040-iobank0-test', 'rp2040-pads-test', 'rp2040-resets-test', 'rp2040-rosc-test', diff --git a/tests/qtest/rp2040-iobank0-test.c b/tests/qtest/rp2040-iobank0-test.c new file mode 100644 index 0000000000..c77baa502e --- /dev/null +++ b/tests/qtest/rp2040-iobank0-test.c @@ -0,0 +1,119 @@ +/* + * QTest testcase for the RP2040 IO_BANK0. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "libqtest.h" +#include "hw/misc/rp2040.h" +#include "qemu/bitops.h" + +#define IOBANK0_BASE 0x40014000 +#define GPIO0_STATUS 0x000 +#define GPIO0_CTRL 0x004 +#define GPIO29_CTRL 0x0ec +#define INTR0 0x0f0 +#define PROC0_INTE0 0x100 +#define PROC0_INTF0 0x110 +#define PROC0_INTS0 0x120 +#define PROC1_INTE3 0x13c +#define PROC1_INTF3 0x14c +#define PROC1_INTS3 0x15c +#define DORMANT_INTE3 0x16c +#define DORMANT_INTF3 0x17c +#define DORMANT_INTS3 0x18c + +#define CTRL_RESET 0x1f +#define CTRL_RW_MASK 0x33333f +#define IRQ_LAST_MASK 0x00ffffff +#define IO_IRQ_BANK0 13 + +#define NVIC_ISPR 0xe000e200 +#define NVIC_ICPR 0xe000e280 + +static QTestState *rp2040_iobank0_start(void) +{ + return qtest_init("-machine raspi-pico"); +} + +static void test_gpio_control(void) +{ + QTestState *qts = rp2040_iobank0_start(); + + g_assert_cmphex(qtest_readl(qts, IOBANK0_BASE + GPIO0_STATUS), ==, 0); + g_assert_cmphex(qtest_readl(qts, IOBANK0_BASE + GPIO0_CTRL), ==, + CTRL_RESET); + g_assert_cmphex(qtest_readl(qts, IOBANK0_BASE + GPIO29_CTRL), ==, + CTRL_RESET); + + qtest_writel(qts, IOBANK0_BASE + GPIO0_CTRL, 0xffffffff); + g_assert_cmphex(qtest_readl(qts, IOBANK0_BASE + GPIO0_CTRL), ==, + CTRL_RW_MASK); + qtest_writel(qts, IOBANK0_BASE + RP2040_ATOMIC_CLR + GPIO0_CTRL, 0x30); + g_assert_cmphex(qtest_readl(qts, IOBANK0_BASE + GPIO0_CTRL), ==, + CTRL_RW_MASK & ~0x30); + qtest_writel(qts, IOBANK0_BASE + RP2040_ATOMIC_XOR + GPIO0_CTRL, 0x03); + g_assert_cmphex(qtest_readl(qts, IOBANK0_BASE + GPIO0_CTRL), ==, + (CTRL_RW_MASK & ~0x30) ^ 0x03); + + qtest_quit(qts); +} + +static void test_proc0_irq(void) +{ + QTestState *qts = rp2040_iobank0_start(); + uint32_t irq = BIT(IO_IRQ_BANK0); + + g_assert_cmphex(qtest_readl(qts, IOBANK0_BASE + INTR0), ==, 0); + g_assert_cmphex(qtest_readl(qts, IOBANK0_BASE + PROC0_INTS0), ==, 0); + g_assert_cmphex(qtest_readl(qts, NVIC_ISPR) & irq, ==, 0); + + qtest_writel(qts, IOBANK0_BASE + PROC0_INTF0, BIT(7)); + g_assert_cmphex(qtest_readl(qts, IOBANK0_BASE + PROC0_INTS0), ==, + BIT(7)); + g_assert_cmphex(qtest_readl(qts, NVIC_ISPR) & irq, ==, irq); + + qtest_writel(qts, IOBANK0_BASE + RP2040_ATOMIC_CLR + PROC0_INTF0, BIT(7)); + g_assert_cmphex(qtest_readl(qts, IOBANK0_BASE + PROC0_INTS0), ==, 0); + qtest_writel(qts, NVIC_ICPR, irq); + g_assert_cmphex(qtest_readl(qts, NVIC_ISPR) & irq, ==, 0); + + qtest_writel(qts, IOBANK0_BASE + RP2040_ATOMIC_SET + PROC0_INTE0, BIT(3)); + g_assert_cmphex(qtest_readl(qts, IOBANK0_BASE + PROC0_INTE0), ==, + BIT(3)); + + qtest_quit(qts); +} + +static void test_last_bank_masks(void) +{ + QTestState *qts = rp2040_iobank0_start(); + + qtest_writel(qts, IOBANK0_BASE + PROC1_INTE3, 0xffffffff); + qtest_writel(qts, IOBANK0_BASE + PROC1_INTF3, 0xffffffff); + g_assert_cmphex(qtest_readl(qts, IOBANK0_BASE + PROC1_INTE3), ==, + IRQ_LAST_MASK); + g_assert_cmphex(qtest_readl(qts, IOBANK0_BASE + PROC1_INTS3), ==, + IRQ_LAST_MASK); + + qtest_writel(qts, IOBANK0_BASE + DORMANT_INTE3, 0xffffffff); + qtest_writel(qts, IOBANK0_BASE + DORMANT_INTF3, 0xffffffff); + g_assert_cmphex(qtest_readl(qts, IOBANK0_BASE + DORMANT_INTE3), ==, + IRQ_LAST_MASK); + g_assert_cmphex(qtest_readl(qts, IOBANK0_BASE + DORMANT_INTS3), ==, + IRQ_LAST_MASK); + + qtest_quit(qts); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + qtest_add_func("/rp2040-iobank0/gpio-control", test_gpio_control); + qtest_add_func("/rp2040-iobank0/proc0-irq", test_proc0_irq); + qtest_add_func("/rp2040-iobank0/last-bank-masks", test_last_bank_masks); + + return g_test_run(); +} -- 2.55.0
