On 9/8/2026 6:08 AM, Andrew Jones wrote:
On Fri, Sep 04, 2026 at 04:56:07PM -0300, Daniel Henrique Barboza wrote:
The harts requirements of RISC-V server platform [1] require RVA23 ISA
profile support and others.
We're going for a profile-based implementation, instead of a regular CPU
that can inherit RVA23, to allow future CPUs to use it internally as a
starting base for their own extension sets. There's also a new
'rvserver-ref-1.0' flag that can be used to set the extensions in the
command line for other CPUs, which can be used for testing/debugging
purposes.
Note that for all intents and purposes "riscv-server-ref" is a regular
CPU and no, we're not trying to set a precedent of calling the riscv
server platform spec a profile.
[1] defines in rule SEE_020 that we must support at least 11 debug
triggers (4 for insn address, 4 for insn load/store, 1 for icount,
one for int, one for excp). We're going for the minimum. If more
triggers are needed users can set any trigger amount with:
-cpu riscv-server-ref,trigger-count=N
Note that N must be <= 128.
[1]
https://github.com/riscv-non-isa/riscv-server-platform/blob/main/server_platform_requirements.adoc
Suggested-by: Icenowy Zheng <[email protected]>
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Matheus Ferst <[email protected]>
Reviewed-by: Chao Liu <[email protected]>
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 31 +++++++++++++++++++++++++++++++
2 files changed, 32 insertions(+)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 1a28f1369c..61234842e3 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -42,6 +42,7 @@
#define TYPE_RISCV_CPU_RVA22S64 RISCV_CPU_TYPE_NAME("rva22s64")
#define TYPE_RISCV_CPU_RVA23U64 RISCV_CPU_TYPE_NAME("rva23u64")
#define TYPE_RISCV_CPU_RVA23S64 RISCV_CPU_TYPE_NAME("rva23s64")
+#define TYPE_RISCV_CPU_RVSERVER_REF RISCV_CPU_TYPE_NAME("riscv-server-ref")
#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
#define TYPE_RISCV_CPU_SIFIVE_E RISCV_CPU_TYPE_NAME("sifive-e")
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 185474a8cf..b5a75fbc1c 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2417,11 +2417,35 @@ static RISCVCPUProfile RVA23S64 = {
}
};
+/*
+ * The riscv-server-ref spec isn't a profile per se but its
spec?
I'll replace this comment with:
"This riscv-server-ref entry isn't a profile per se but ..."
+ * CPU definition can be modelled as a profile that extends
+ * RVA23, with additional things on top of it, and allowing
+ * future CPUs to derive from it via
+ * ".profile = &RVServerRef1_0;".
+ */
+static RISCVCPUProfile RVServerRef1_0 = {
+ .s_parent = &RVA23S64,
+ .name = "rvserver-ref-1.0",
The commit message and comment call this "riscv-server-ref"
The CPU is called riscv-server-ref:
#define TYPE_RISCV_CPU_RVSERVER_REF RISCV_CPU_TYPE_NAME("riscv-server-ref")
"rvserver-ref-1.0" is the CPU profile name I came up with as a placeholder. I
believe we can rename it to "riscv-server-ref-1.0" to avoid confusion.
+ .satp_mode = VM_1_10_SV48,
+ .ext_offsets = {
+ CPU_CFG_OFFSET(ext_zkr),
+ CPU_CFG_OFFSET(ext_sdtrig),
+ CPU_CFG_OFFSET(ext_ssaia),
+ CPU_CFG_OFFSET(ext_ssccfg),
The cover letter says that the sdext patches need to be merged first.
Don't we need to configure it here?
Yeah ... we had a very earlier version where enabling sdtrig implied enabling
sdext.
That's not the case for some time now and forgot to manually add 'sdext' here.
I'll do that. Thanks,
Daniel
+ /* ssstrict is always enabled for PRIV_VER_1_12 */
+
+ RISCV_PROFILE_EXT_LIST_END
+ }
+};
+
+
RISCVCPUProfile *riscv_profiles[] = {
&RVA22U64,
&RVA22S64,
&RVA23U64,
&RVA23S64,
+ &RVServerRef1_0,
NULL,
};
@@ -3759,6 +3783,13 @@ static const TypeInfo riscv_cpu_type_infos[] = {
#endif
),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RVSERVER_REF, TYPE_RISCV_BARE_CPU,
+ .profile = &RVServerRef1_0,
+ .misa_mxl_max = MXL_RV64,
+ .cfg.max_satp_mode = VM_1_10_SV57,
+ .num_triggers = 11,
+ ),
+
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU,
.cfg.max_satp_mode = VM_1_10_SV57,
--
2.43.0
Thanks,
drew
