On Sat, Sep 5, 2026 at 1:27 AM Daniel Henrique Barboza
<[email protected]> wrote:
>
> The harts requirements of RISC-V server platform [1] require RVA23 ISA
> profile support and others.
>
> We're going for a profile-based implementation, instead of a regular CPU
> that can inherit RVA23, to allow future CPUs to use it internally as a
> starting base for their own extension sets. There's also a new
> 'rvserver-ref-1.0' flag that can be used to set the extensions in the
> command line for other CPUs, which can be used for testing/debugging
> purposes.
>
> Note that for all intents and purposes "riscv-server-ref" is a regular
> CPU and no, we're not trying to set a precedent of calling the riscv
> server platform spec a profile.
>
> [1] defines in rule SEE_020 that we must support at least 11 debug
> triggers (4 for insn address, 4 for insn load/store, 1 for icount,
> one for int, one for excp). We're going for the minimum. If more
> triggers are needed users can set any trigger amount with:
>
> -cpu riscv-server-ref,trigger-count=N
>
> Note that N must be <= 128.
>
> [1]
> https://github.com/riscv-non-isa/riscv-server-platform/blob/main/server_platform_requirements.adoc
>
> Suggested-by: Icenowy Zheng <[email protected]>
> Signed-off-by: Daniel Henrique Barboza <[email protected]>
> Reviewed-by: Alistair Francis <[email protected]>
> Reviewed-by: Matheus Ferst <[email protected]>
> Reviewed-by: Chao Liu <[email protected]>
> ---
> target/riscv/cpu-qom.h | 1 +
> target/riscv/cpu.c | 31 +++++++++++++++++++++++++++++++
> 2 files changed, 32 insertions(+)
>
Reviewed-by: Sunil V L <[email protected]>
