We previously allowed the GICv5 on any 64-bit CPU, with a hack where enabling the GICv5 silently disabled AArch32 for EL1..3.
Now that we have a separate 'max-v8' and 'max-v9' where max-v9 correctly doesn't implement AArch32 at EL1..3, we can fix the "when do we expose the has_gcie property" condition so that we only allow the GICv5 when AArch32 doesn't exist above EL0, and remove the hack disabling AArch32. We could instead have defined a new ARM_FEATURE_V9, but "allow the feature to be present on CPUs where it doesn't actively break anything" fits the way we've generally handled things in QEMU, and it avoids having a new V9 feature bit that we only use for this one thing and where it's not clear when we should be setting it for KVM, hvf, etc accelerators. In practice the only CPUs which will allow GICv5 now are max, max-v9 and a64fx. Signed-off-by: Peter Maydell <[email protected]> --- target/arm/cpu-features.h | 8 ++++++++ target/arm/cpu.c | 37 +++++++------------------------------ 2 files changed, 15 insertions(+), 30 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index eecbc3b889e..c4029c0f73c 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1129,6 +1129,14 @@ static inline bool isar_feature_aa64_aa32_el3(const ARMISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL3) >= 2; } +static inline bool isar_feature_aa64_aa32_above_el0(const ARMISARegisters *id) +{ + /* True if any EL above EL0 has AArch32 support */ + return isar_feature_aa64_aa32_el1(id) || + isar_feature_aa64_aa32_el2(id) || + isar_feature_aa64_aa32_el3(id); +} + static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64PFR0, RAS) != 0; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2b1b87b0ed4..bbf4e0aa465 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1584,8 +1584,13 @@ static void arm_cpu_post_init(Object *obj) &cpu->rvbar_prop, OBJ_PROP_FLAG_READWRITE); - /* We only allow GICv5 on a 64-bit v8 CPU */ - if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + /* + * We only allow GICv5 on a CPU with no AArch32 support above EL0 + * (which is typically a v9 CPU), because GICv5 defines no AArch32 + * system registers to control it. + */ + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && + !cpu_isar_feature(aa64_aa32_above_el0, cpu)) { qdev_property_add_static(DEVICE(obj), &arm_cpu_has_gcie_property); } } @@ -2235,34 +2240,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) /* Report FEAT_GCIE in our ID registers if property was set */ FIELD_DP64_IDREG(isar, ID_AA64PFR2, GCIE, cpu->has_gcie); - if (cpu_isar_feature(aa64_gcie, cpu)) { - if (!arm_feature(env, ARM_FEATURE_AARCH64)) { - /* - * We only create the have_gcie property for AArch64 CPUs, - * but the user might have tried aarch64=off with has_gcie=on. - */ - error_setg(errp, "Cannot both enable has_gcie and disable aarch64"); - return; - } - - /* - * FEAT_GCIE implies Armv9, which implies no AArch32 above EL0. - * Usually we don't strictly insist on this kind of feature - * dependency, but in this case we enforce it, because the - * GICv5 CPU interface has no AArch32 versions of its system - * registers, so interrupts wouldn't work if we allowed AArch32 - * in EL1 or above. Downgrade "AArch32 and AArch64" to "AArch64". - */ - if (cpu_isar_feature(aa64_aa32_el3, cpu)) { - FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL3, 1); - } - if (cpu_isar_feature(aa64_aa32_el2, cpu)) { - FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL2, 1); - } - if (cpu_isar_feature(aa64_aa32_el1, cpu)) { - FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL1, 1); - } - } if (cpu_isar_feature(aa64_mte, cpu)) { /* -- 2.43.0
