Since the function is exposed through the cpu.h header, make sure it's rv32/rv64 agnostic. Note return type could be made uint32_t and arguments dropped, but I chose to follow the existing CSR OP style of functions, in case there are other plans for this one.
Signed-off-by: Anton Johansson <[email protected]> --- target/riscv/cpu.h | 4 ++-- target/riscv/cpu.c | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a820ec2f6e..a5fb75b990 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -953,8 +953,8 @@ void riscv_add_satp_mode_properties(Object *obj); bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu); void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); -target_ulong riscv_new_csr_seed(target_ulong new_value, - target_ulong write_mask); +uint64_t riscv_new_csr_seed(uint64_t new_value, + uint64_t write_mask); const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); const char *priv_spec_to_str(int priv_version); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4f58e91b62..3356ba61d2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -546,13 +546,13 @@ static void set_satp_mode_default_map(RISCVCPU *cpu) #endif /* Used by csr.c and the KVM driver */ -target_ulong riscv_new_csr_seed(target_ulong new_value, - target_ulong write_mask) +uint64_t riscv_new_csr_seed(uint64_t new_value, + uint64_t write_mask) { uint16_t random_v; Error *random_e = NULL; int random_r; - target_ulong rval; + uint64_t rval; random_r = qemu_guest_getrandom(&random_v, 2, &random_e); if (unlikely(random_r < 0)) { -- 2.52.0
