On 9/16/2026 2:19 AM, Anton Johansson wrote:
> Filters for 32- or 64-bit machine types using TypeInfo::is_available,
> machines available for both 32-bit and 64-bit (amd-microblaze-v-generic,
> sifive-[e|u], spike, virt) leave the field unset.
>
> Signed-off-by: Anton Johansson <[email protected]>
> ---
> hw/riscv/boston-aia.c | 3 ++-
> hw/riscv/k230.c | 3 +++
> hw/riscv/microchip_pfsoc.c | 3 +++
> hw/riscv/opentitan.c | 3 +++
> hw/riscv/shakti_c.c | 3 +++
> hw/riscv/tt_atlantis.c | 3 +++
> hw/riscv/xiangshan_kmh.c | 3 +++
> 7 files changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/hw/riscv/boston-aia.c b/hw/riscv/boston-aia.c
> index b90da096ea..e8371ff1f1 100644
> --- a/hw/riscv/boston-aia.c
> +++ b/hw/riscv/boston-aia.c
> @@ -10,6 +10,7 @@
> */
>
> #include "qemu/osdep.h"
> +#include "qemu/target-info.h"
> #include "qemu/units.h"
>
> #include "hw/core/boards.h"
> @@ -473,4 +474,4 @@ static void boston_mach_class_init(MachineClass *mc)
> mc->default_cpu_type = TYPE_RISCV_CPU_MIPS_P8700;
> }
>
> -DEFINE_MACHINE("boston-aia", boston_mach_class_init)
> +DEFINE_MACHINE_WITH_GUARD("boston-aia", boston_mach_class_init,
> target_riscv64)
Convert that to a "full" declaration, and add is_available on the way.
> diff --git a/hw/riscv/k230.c b/hw/riscv/k230.c
> index 1e4ca38579..43b6ae6d2f 100644
> --- a/hw/riscv/k230.c
> +++ b/hw/riscv/k230.c
> @@ -17,6 +17,7 @@
> #include "cpu-qom.h"
> #include "qemu/cutils.h"
> #include "qemu/error-report.h"
> +#include "qemu/target-info.h"
> #include "qapi/error.h"
> #include "system/device_tree.h"
> #include "system/system.h"
> @@ -420,6 +421,7 @@ static const TypeInfo k230_soc_type_info = {
> .instance_size = sizeof(K230SoCState),
> .instance_init = k230_soc_init,
> .class_init = k230_soc_class_init,
> + .is_available = target_riscv64,
> };
>
> static void k230_soc_register_types(void)
> @@ -558,6 +560,7 @@ static const TypeInfo k230_machine_typeinfo = {
> .class_init = k230_machine_class_init,
> .instance_init = k230_machine_instance_init,
> .instance_size = sizeof(K230MachineState),
> + .is_available = target_riscv64,
> };
>
> static void k230_machine_init_register_types(void)
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index edd29626fa..b2991e5a71 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -38,6 +38,7 @@
> #include "qemu/error-report.h"
> #include "qemu/units.h"
> #include "qemu/cutils.h"
> +#include "qemu/target-info.h"
> #include "qapi/error.h"
> #include "qapi/visitor.h"
> #include "hw/core/boards.h"
> @@ -504,6 +505,7 @@ static const TypeInfo microchip_pfsoc_soc_type_info = {
> .instance_size = sizeof(MicrochipPFSoCState),
> .instance_init = microchip_pfsoc_soc_instance_init,
> .class_init = microchip_pfsoc_soc_class_init,
> + .is_available = target_riscv64,
> };
>
> static void microchip_pfsoc_soc_register_types(void)
> @@ -757,6 +759,7 @@ static const TypeInfo
> microchip_icicle_kit_machine_typeinfo = {
> .class_init = microchip_icicle_kit_machine_class_init,
> .instance_init = microchip_icicle_kit_machine_instance_init,
> .instance_size = sizeof(MicrochipIcicleKitState),
> + .is_available = target_riscv64,
> };
>
> static void microchip_icicle_kit_machine_init_register_types(void)
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index 8cd660dd41..c3a563db92 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -20,6 +20,7 @@
>
> #include "qemu/osdep.h"
> #include "qemu/cutils.h"
> +#include "qemu/target-info.h"
> #include "hw/riscv/opentitan.h"
> #include "qapi/error.h"
> #include "qemu/error-report.h"
> @@ -332,11 +333,13 @@ static const TypeInfo open_titan_types[] = {
> .instance_size = sizeof(LowRISCIbexSoCState),
> .instance_init = lowrisc_ibex_soc_init,
> .class_init = lowrisc_ibex_soc_class_init,
> + .is_available = target_riscv32,
> }, {
> .name = TYPE_OPENTITAN_MACHINE,
> .parent = TYPE_MACHINE,
> .instance_size = sizeof(OpenTitanState),
> .class_init = opentitan_machine_class_init,
> + .is_available = target_riscv32,
> }
> };
>
> diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
> index 3b6efd25be..76cfe30918 100644
> --- a/hw/riscv/shakti_c.c
> +++ b/hw/riscv/shakti_c.c
> @@ -21,6 +21,7 @@
> #include "hw/riscv/shakti_c.h"
> #include "qapi/error.h"
> #include "qemu/error-report.h"
> +#include "qemu/target-info.h"
> #include "hw/intc/sifive_plic.h"
> #include "hw/intc/riscv_aclint.h"
> #include "system/system.h"
> @@ -97,6 +98,7 @@ static const TypeInfo shakti_c_machine_type_info = {
> .class_init = shakti_c_machine_class_init,
> .instance_init = shakti_c_machine_instance_init,
> .instance_size = sizeof(ShaktiCMachineState),
> + .is_available = target_riscv64,
> };
>
> static void shakti_c_machine_type_info_register(void)
> @@ -186,6 +188,7 @@ static const TypeInfo shakti_c_type_info = {
> .class_init = shakti_c_soc_class_init,
> .instance_init = shakti_c_soc_instance_init,
> .instance_size = sizeof(ShaktiCSoCState),
> + .is_available = target_riscv64,
> };
>
> static void shakti_c_type_info_register(void)
> diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c
> index b2333e7f6a..f54eb942f3 100644
> --- a/hw/riscv/tt_atlantis.c
> +++ b/hw/riscv/tt_atlantis.c
> @@ -11,6 +11,7 @@
> #include "qemu/cutils.h"
> #include "qemu/error-report.h"
> #include "qemu/guest-random.h"
> +#include "qemu/target-info.h"
> #include "qemu/units.h"
>
> #include "hw/core/boards.h"
> @@ -694,11 +695,13 @@ static const TypeInfo tt_atlantis_types[] = {
> .instance_size = sizeof(TTAtlantisSoCState),
> .instance_init = tt_atlantis_soc_init,
> .class_init = tt_atlantis_soc_class_init,
> + .is_available = target_riscv64,
> }, {
> .name = MACHINE_TYPE_NAME("tt-atlantis"),
> .parent = TYPE_MACHINE,
> .class_init = tt_atlantis_machine_class_init,
> .instance_size = sizeof(TTAtlantisState),
> + .is_available = target_riscv64,
> },
> };
>
> diff --git a/hw/riscv/xiangshan_kmh.c b/hw/riscv/xiangshan_kmh.c
> index a234c5f352..f2383c5399 100644
> --- a/hw/riscv/xiangshan_kmh.c
> +++ b/hw/riscv/xiangshan_kmh.c
> @@ -30,6 +30,7 @@
> */
>
> #include "qemu/osdep.h"
> +#include "qemu/target-info.h"
> #include "qapi/error.h"
> #include "system/address-spaces.h"
> #include "hw/core/boards.h"
> @@ -157,6 +158,7 @@ static const TypeInfo xiangshan_kmh_soc_info = {
> .instance_size = sizeof(XiangshanKmhSoCState),
> .instance_init = xiangshan_kmh_soc_instance_init,
> .class_init = xiangshan_kmh_soc_class_init,
> + .is_available = target_riscv64,
> };
>
> static void xiangshan_kmh_soc_register_types(void)
> @@ -220,6 +222,7 @@ static const TypeInfo xiangshan_kmh_machine_info = {
> .parent = TYPE_MACHINE,
> .instance_size = sizeof(XiangshanKmhState),
> .class_init = xiangshan_kmh_machine_class_init,
> + .is_available = target_riscv64,
> };
>
> static void xiangshan_kmh_machine_register_types(void)
>
