As I said before, we need the `const TargetInfo*` parameter to for is_avaiable. I've get all accelerator and i386/x86_64/aarch64/arm/risv32/riscv64/
single_binary_supported_targets = [ 'aarch64-softmmu', 'arm-softmmu', + 'i386-softmmu', 'microblaze-softmmu', 'riscv32-softmmu', 'riscv64-softmmu', + 'x86_64-softmmu', ] On Thu, Sep 17, 2026 at 1:03 AM Pierrick Bouvier < [email protected]> wrote: > > On 9/16/2026 2:19 AM, Anton Johansson wrote: > > Will be used in the following commit to filter machines using > > TypeInfo::is_available, so a simple !target_riscv64() is not sufficient. > > > > Signed-off-by: Anton Johansson <[email protected]> > > --- > > include/qemu/target-info.h | 7 +++++++ > > target-info.c | 5 +++++ > > 2 files changed, 12 insertions(+) > > > > Reviewed-by: Pierrick Bouvier <[email protected]> > include/qemu/target-info.h | 30 ++++++++++++++++++++++++++++++ target-info.c | 26 ++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h index 0620a3db84..560d589bcf 100644 --- a/include/qemu/target-info.h +++ b/include/qemu/target-info.h @@ -239,6 +239,36 @@ bool target_is_s390x(const TargetInfo *ti); */ bool target_s390x(void); +/** + * target_is_base_riscv: + * @ti: TargetInfo to inspect + * + * Returns whether @ti is RISC-V 32-bit or 64-bit. + */ +bool target_is_base_riscv(const TargetInfo *ti); + +/** + * target_base_riscv: + * + * Returns whether the target architecture is RISC-V 32-bit or 64-bit. + */ +bool target_base_riscv(void); + +/** + * target_is_riscv32: + * @ti: TargetInfo to inspect + * + * Returns whether @ti is RISC-V 32-bit. + */ +bool target_is_riscv32(const TargetInfo *ti); + +/** + * target_riscv32: + * + * Returns whether the target architecture is RISC-V 32-bit. + */ +bool target_riscv32(void); + /** * target_is_riscv64: * @ti: TargetInfo to inspect diff --git a/target-info.c b/target-info.c index 9083b7bca6..a9fcd1c07b 100644 --- a/target-info.c +++ b/target-info.c @@ -250,6 +250,32 @@ bool target_s390x(void) return target_is_s390x(target_info()); } +bool target_is_base_riscv(const TargetInfo *ti) +{ + switch (ti->target_arch) { + case SYS_EMU_TARGET_RISCV32: + case SYS_EMU_TARGET_RISCV64: + return true; + default: + return false; + } +} + +bool target_base_riscv(void) +{ + return target_is_base_riscv(target_info()); +} + +bool target_is_riscv32(const TargetInfo *ti) +{ + return ti->target_arch == SYS_EMU_TARGET_RISCV32; +} + +bool target_riscv32(void) +{ + return target_is_riscv32(target_info()); +} + bool target_is_riscv64(const TargetInfo *ti) { return ti->target_arch == SYS_EMU_TARGET_RISCV64; These are the helpers I needed, that are very important.for subsequent work, otherwise the latter work will be repeated again. and split target_is_* out again. Those is_avaiable should use target_is_*, that's differ from target_riscv32 and so on. -- 此致 礼 罗勇刚 Yours sincerely, Yonggang Luo
