Currently the MTE feature tests are clustered together, but those are spread across two ID registers. Sort the functions by ID reg and bitfield order, like most others.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]> Signed-off-by: Richard Henderson <[email protected]> --- target/arm/cpu-features.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index eecbc3b889e..06318d12f9f 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1207,16 +1207,6 @@ static inline bool isar_feature_aa64_mte3(const ARMISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64PFR1, MTE) >= 3; } -static inline bool isar_feature_aa64_mteperm(const ARMISARegisters *id) -{ - return FIELD_EX64_IDREG(id, ID_AA64PFR2, MTEPERM) >= 1; -} - -static inline bool isar_feature_aa64_mte_store_only(const ARMISARegisters *id) -{ - return FIELD_EX64_IDREG(id, ID_AA64PFR2, MTESTOREONLY) == 1; -} - static inline bool isar_feature_aa64_mte_mtx(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64PFR1, MTEX) != 0; @@ -1237,6 +1227,16 @@ static inline bool isar_feature_aa64_gcs(const ARMISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64PFR1, GCS) != 0; } +static inline bool isar_feature_aa64_mteperm(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64PFR2, MTEPERM) >= 1; +} + +static inline bool isar_feature_aa64_mte_store_only(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64PFR2, MTESTOREONLY) == 1; +} + static inline bool isar_feature_aa64_gcie(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64PFR2, GCIE) != 0; -- 2.53.0
