Replaces uses of target_ulong with fixed-size integers, this is a
prerequisite step to compiling cpu.c once for system-mode.
Note: the widening of target_long to int64_t in adjust_addr_body() is
safe as rv32 is ruled out earlier in the function via the check
/* do nothing for rv32 mode */
if (riscv_cpu_mxl(env) == MXL_RV32) {
return addr;
}
meaning target_long must be equal to int64_t anyway.
Duplicate includes between vector_helper.c and vector_internals.h are
removed.
Signed-off-by: Anton Johansson <[email protected]>
---
target/riscv/internals.h | 31 +++++++++---------
target/riscv/tcg/vector_internals.h | 5 +--
target/riscv/tcg/vector_helper.c | 64 +++++++++++++++++--------------------
3 files changed, 47 insertions(+), 53 deletions(-)
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 1ee7e99e98..c963fae321 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -20,7 +20,6 @@
#define RISCV_CPU_INTERNALS_H
#include "exec/cpu-common.h"
-#include "exec/target_long.h"
#include "hw/core/registerfields.h"
#include "fpu/softfloat-types.h"
#include "target/riscv/cpu_bits.h"
@@ -98,10 +97,10 @@ FIELD(VDATA, NF, 7, 4)
FIELD(VDATA, WD, 7, 1)
/* float point classify helpers */
-target_ulong fclass_h_bf16(uint64_t frs1);
-target_ulong fclass_h(uint64_t frs1);
-target_ulong fclass_s(uint64_t frs1);
-target_ulong fclass_d(uint64_t frs1);
+uint16_t fclass_h_bf16(bfloat16 frs1);
+uint16_t fclass_h(float16 frs1);
+uint16_t fclass_s(float32 frs1);
+uint16_t fclass_d(float64 frs1);
#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_riscv_cpu;
@@ -185,7 +184,7 @@ static inline float16 check_nanbox_bf16(CPURISCVState *env,
uint64_t f)
}
}
-static inline target_ulong get_xepc_mask(CPURISCVState *env)
+static inline uint64_t get_xepc_mask(CPURISCVState *env)
{
RISCVCPU *cpu = env_archcpu(env);
@@ -196,9 +195,9 @@ static inline target_ulong get_xepc_mask(CPURISCVState *env)
if (riscv_has_ext(env, RVC) || cpu->cfg.ext_zca ||
cpu->cfg.ext_zcb || cpu->cfg.ext_zcd || cpu->cfg.ext_zce ||
cpu->cfg.ext_zcf || cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) {
- return ~(target_ulong)1;
+ return ~1ull;
} else {
- return ~(target_ulong)3;
+ return ~3ull;
}
}
@@ -208,9 +207,9 @@ bool riscv_cpu_has_work(CPUState *cs);
#endif
/* Zjpm addr masking routine */
-static inline target_ulong adjust_addr_body(CPURISCVState *env,
- target_ulong addr,
- bool is_virt_addr)
+static inline uint64_t adjust_addr_body(CPURISCVState *env,
+ uint64_t addr,
+ bool is_virt_addr)
{
RISCVPmPmm pmm = PMM_FIELD_DISABLED;
uint32_t pmlen = 0;
@@ -239,7 +238,7 @@ static inline target_ulong adjust_addr_body(CPURISCVState
*env,
/* sign/zero extend masked address by N-1 bit */
if (signext) {
- addr = (target_long)addr >> pmlen;
+ addr = (int64_t)addr >> pmlen;
} else {
addr = addr >> pmlen;
}
@@ -247,14 +246,14 @@ static inline target_ulong adjust_addr_body(CPURISCVState
*env,
return addr;
}
-static inline target_ulong adjust_addr(CPURISCVState *env,
- target_ulong addr)
+static inline uint64_t adjust_addr(CPURISCVState *env,
+ uint64_t addr)
{
return adjust_addr_body(env, addr, false);
}
-static inline target_ulong adjust_addr_virt(CPURISCVState *env,
- target_ulong addr)
+static inline uint64_t adjust_addr_virt(CPURISCVState *env,
+ uint64_t addr)
{
return adjust_addr_body(env, addr, true);
}
diff --git a/target/riscv/tcg/vector_internals.h
b/target/riscv/tcg/vector_internals.h
index 5681b81815..7e186add2d 100644
--- a/target/riscv/tcg/vector_internals.h
+++ b/target/riscv/tcg/vector_internals.h
@@ -20,10 +20,11 @@
#define TARGET_RISCV_VECTOR_INTERNALS_H
#include "qemu/bitops.h"
+#include "exec/target_long.h"
#include "hw/core/registerfields.h"
-#include "cpu.h"
+#include "target/riscv/cpu.h"
+#include "target/riscv/internals.h"
#include "tcg/tcg-gvec-desc.h"
-#include "internals.h"
#define VSTART_CHECK_EARLY_EXIT(env, vl) do { \
if (env->vstart >= vl) { \
diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
index 0d1e4e0964..b4a07dbe13 100644
--- a/target/riscv/tcg/vector_helper.c
+++ b/target/riscv/tcg/vector_helper.c
@@ -19,7 +19,7 @@
#include "qemu/osdep.h"
#include "qemu/host-utils.h"
#include "qemu/bitops.h"
-#include "cpu.h"
+#include "target/riscv/tcg/vector_internals.h"
#include "exec/memop.h"
#include "accel/tcg/cpu-ldst.h"
#include "accel/tcg/probe.h"
@@ -29,8 +29,6 @@
#include "exec/target_page.h"
#include "fpu/softfloat.h"
#include "tcg/tcg-gvec-desc.h"
-#include "internals.h"
-#include "vector_internals.h"
#include <math.h>
static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)
@@ -4852,77 +4850,73 @@ GEN_VEXT_CMP_VF(vmfge_vf_w, uint32_t, H4, vmfge32)
GEN_VEXT_CMP_VF(vmfge_vf_d, uint64_t, H8, vmfge64)
/* Vector Floating-Point Classify Instruction */
-target_ulong fclass_h_bf16(uint64_t frs1)
+uint16_t fclass_h_bf16(bfloat16 frs1)
{
- bfloat16 f = frs1;
- bool sign = bfloat16_is_neg(f);
+ bool sign = bfloat16_is_neg(frs1);
- if (bfloat16_is_infinity(f)) {
+ if (bfloat16_is_infinity(frs1)) {
return sign ? 1 << 0 : 1 << 7;
- } else if (bfloat16_is_zero(f)) {
+ } else if (bfloat16_is_zero(frs1)) {
return sign ? 1 << 3 : 1 << 4;
- } else if (bfloat16_is_zero_or_denormal(f)) {
+ } else if (bfloat16_is_zero_or_denormal(frs1)) {
return sign ? 1 << 2 : 1 << 5;
- } else if (bfloat16_is_any_nan(f)) {
+ } else if (bfloat16_is_any_nan(frs1)) {
float_status s = { }; /* for snan_bit_is_one */
- return bfloat16_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8;
+ return bfloat16_is_quiet_nan(frs1, &s) ? 1 << 9 : 1 << 8;
} else {
return sign ? 1 << 1 : 1 << 6;
}
}
-target_ulong fclass_h(uint64_t frs1)
+uint16_t fclass_h(float16 frs1)
{
- float16 f = frs1;
- bool sign = float16_is_neg(f);
+ bool sign = float16_is_neg(frs1);
- if (float16_is_infinity(f)) {
+ if (float16_is_infinity(frs1)) {
return sign ? 1 << 0 : 1 << 7;
- } else if (float16_is_zero(f)) {
+ } else if (float16_is_zero(frs1)) {
return sign ? 1 << 3 : 1 << 4;
- } else if (float16_is_zero_or_denormal(f)) {
+ } else if (float16_is_zero_or_denormal(frs1)) {
return sign ? 1 << 2 : 1 << 5;
- } else if (float16_is_any_nan(f)) {
+ } else if (float16_is_any_nan(frs1)) {
float_status s = { }; /* for snan_bit_is_one */
- return float16_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8;
+ return float16_is_quiet_nan(frs1, &s) ? 1 << 9 : 1 << 8;
} else {
return sign ? 1 << 1 : 1 << 6;
}
}
-target_ulong fclass_s(uint64_t frs1)
+uint16_t fclass_s(float32 frs1)
{
- float32 f = frs1;
- bool sign = float32_is_neg(f);
+ bool sign = float32_is_neg(frs1);
- if (float32_is_infinity(f)) {
+ if (float32_is_infinity(frs1)) {
return sign ? 1 << 0 : 1 << 7;
- } else if (float32_is_zero(f)) {
+ } else if (float32_is_zero(frs1)) {
return sign ? 1 << 3 : 1 << 4;
- } else if (float32_is_zero_or_denormal(f)) {
+ } else if (float32_is_zero_or_denormal(frs1)) {
return sign ? 1 << 2 : 1 << 5;
- } else if (float32_is_any_nan(f)) {
+ } else if (float32_is_any_nan(frs1)) {
float_status s = { }; /* for snan_bit_is_one */
- return float32_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8;
+ return float32_is_quiet_nan(frs1, &s) ? 1 << 9 : 1 << 8;
} else {
return sign ? 1 << 1 : 1 << 6;
}
}
-target_ulong fclass_d(uint64_t frs1)
+uint16_t fclass_d(float64 frs1)
{
- float64 f = frs1;
- bool sign = float64_is_neg(f);
+ bool sign = float64_is_neg(frs1);
- if (float64_is_infinity(f)) {
+ if (float64_is_infinity(frs1)) {
return sign ? 1 << 0 : 1 << 7;
- } else if (float64_is_zero(f)) {
+ } else if (float64_is_zero(frs1)) {
return sign ? 1 << 3 : 1 << 4;
- } else if (float64_is_zero_or_denormal(f)) {
+ } else if (float64_is_zero_or_denormal(frs1)) {
return sign ? 1 << 2 : 1 << 5;
- } else if (float64_is_any_nan(f)) {
+ } else if (float64_is_any_nan(frs1)) {
float_status s = { }; /* for snan_bit_is_one */
- return float64_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8;
+ return float64_is_quiet_nan(frs1, &s) ? 1 << 9 : 1 << 8;
} else {
return sign ? 1 << 1 : 1 << 6;
}
--
2.52.0
