On 1/10/26 17:59, Anton Johansson wrote:
Replaces uses of target_ulong with vaddr/hwaddr/uint64_t where
appropriate.
Note: This commit will print all addresses as 64-bit values, even for a
32-bit target. If breaking this interface is not an option we can
instead opt for more runtime branching, as done by Joel Stanley
in commit 409c7d8682a.
This is just about passing @width... mem_info_svxx() already gets MXL.
Signed-off-by: Anton Johansson <[email protected]>
---
target/riscv/monitor.c | 42 ++++++++++++++++++------------------------
target/riscv/meson.build | 2 +-
2 files changed, 19 insertions(+), 25 deletions(-)
-#ifdef TARGET_RISCV64
#define PTE_HEADER_FIELDS "vaddr paddr "\
"size attr\n"
#define PTE_HEADER_DELIMITER "---------------- ---------------- "\
"---------------- -------\n"
-#else
-#define PTE_HEADER_FIELDS "vaddr paddr size attr\n"
-#define PTE_HEADER_DELIMITER "-------- ---------------- -------- -------\n"
Otherwise unifying this header LGTM.
-#endif
@@ -158,10 +152,10 @@ static void mem_info_svxx(MonitorHMP *hmp, CPUArchState
*env)
AddressSpace *as = env_cpu(env)->as;
int levels, ptidxbits, ptesize, vm, va_bits;
hwaddr base;
- target_ulong vbase;
+ vaddr vbase;
hwaddr pbase;
hwaddr last_paddr;
- target_ulong last_size;
+ uint64_t last_size;
int last_attr;
if (riscv_cpu_mxl(env) == MXL_RV32) {
^^^
