[PATCH 12/18] target/riscv: Compile tcg-cpu.c once for system-mode

[Anton Johansson via qemu development]

Remaining target_ulongs are replaced by their corresponding type in
CPUArchState.

Signed-off-by: Anton Johansson <a...@rev.ng>
---
 target/riscv/tcg/tcg-cpu.c   | 8 ++++----
 target/riscv/tcg/meson.build | 3 ++-
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index b68160af83..91b2e128ea 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -229,7 +229,7 @@ static void riscv_restore_state_to_opc(CPUState *cs,
     RISCVCPU *cpu = RISCV_CPU(cs);
     CPURISCVState *env = &cpu->env;
     RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
-    target_ulong pc;
+    uint64_t pc;
 
     if (tb_cflags(tb) & CF_PCREL) {
         pc = (env->pc & TARGET_PAGE_MASK) | data[0];
@@ -1336,7 +1336,7 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error 
**errp)
 }
 
 typedef struct RISCVCPUMisaExtConfig {
-    target_ulong misa_bit;
+    uint32_t misa_bit;
     bool enabled;
 } RISCVCPUMisaExtConfig;
 
@@ -1344,7 +1344,7 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, 
const char *name,
                                  void *opaque, Error **errp)
 {
     const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
-    target_ulong misa_bit = misa_ext_cfg->misa_bit;
+    uint32_t misa_bit = misa_ext_cfg->misa_bit;
     RISCVCPU *cpu = RISCV_CPU(obj);
     CPURISCVState *env = &cpu->env;
     bool vendor_cpu = riscv_cpu_is_vendor(obj);
@@ -1386,7 +1386,7 @@ static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, 
const char *name,
                                  void *opaque, Error **errp)
 {
     const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
-    target_ulong misa_bit = misa_ext_cfg->misa_bit;
+    uint32_t misa_bit = misa_ext_cfg->misa_bit;
     RISCVCPU *cpu = RISCV_CPU(obj);
     CPURISCVState *env = &cpu->env;
     bool value;
diff --git a/target/riscv/tcg/meson.build b/target/riscv/tcg/meson.build
index cc50f3764c..69dadfd662 100644
--- a/target/riscv/tcg/meson.build
+++ b/target/riscv/tcg/meson.build
@@ -9,7 +9,6 @@ riscv_ss.add(files(
   'm128_helper.c',
   'op_helper.c',
   'translate.c',
-  'tcg-cpu.c',
   'vcrypto_helper.c',
   'vector_helper.c',
   'vector_internals.c',
@@ -25,6 +24,7 @@ riscv_system_ss.add(files(
 riscv_user_ss.add(files(
   'cpu_helper.c',
   'csr.c',
+  'tcg-cpu.c',
 ))
 
 
@@ -33,5 +33,6 @@ riscv_common_system_ss.add(files(
   'csr.c',
   'mips_csr.c',
   'pmu.c',
+  'tcg-cpu.c',
   'th_csr.c',
 ))

-- 
2.52.0