FU540 SoC has a 2MiB L2 cache, so the maximum mapped size of L2LIM should be set to 2MiB too.
Signed-off-by: Bin Meng <[email protected]> --- Changes in v3: - New hw/riscv/sifive_u.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index b7d5e7b4da..1ac0d1bbd9 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -72,7 +72,7 @@ static const MemMapEntry sifive_u_memmap[] = { [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 }, [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 }, [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 }, - [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 }, + [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x200000 }, [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 }, [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 }, [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 }, -- 2.53.0
