The Icicle Kit memory map advertises the PolarFire RTC, but the machine leaves its MMIO range unmapped. Linux faults when it programs the RTC prescaler during boot.
Select and instantiate the RTC, map it at the documented address, and wire its wakeup and match outputs to PLIC interrupts 80 and 81. Signed-off-by: Bin Meng <[email protected]> Reviewed-by: Chao Liu <[email protected]> --- (no changes since v1) include/hw/riscv/microchip_pfsoc.h | 4 ++++ hw/riscv/microchip_pfsoc.c | 11 +++++++++++ hw/riscv/Kconfig | 1 + 3 files changed, 16 insertions(+) diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h index 18f5003850..5827d6be2f 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -31,6 +31,7 @@ #include "hw/misc/mchp_pfsoc_ioscb.h" #include "hw/misc/mchp_pfsoc_sysreg.h" #include "hw/net/cadence_gem.h" +#include "hw/rtc/mchp_pfsoc_rtc.h" #include "hw/sd/cadence_sdhci.h" #include "hw/riscv/riscv_hart.h" @@ -53,6 +54,7 @@ typedef struct MicrochipPFSoCState { MchpPfSoCMMUartState *serial2; MchpPfSoCMMUartState *serial3; MchpPfSoCMMUartState *serial4; + MchpPfSoCRtcState rtc; MchpPfSoCSysregState sysreg; SiFivePDMAState dma; CadenceGEMState gem0; @@ -148,6 +150,8 @@ enum { MICROCHIP_PFSOC_DMA_IRQ7 = 12, MICROCHIP_PFSOC_GEM0_IRQ = 64, MICROCHIP_PFSOC_GEM1_IRQ = 70, + MICROCHIP_PFSOC_RTC_WAKEUP_IRQ = 80, + MICROCHIP_PFSOC_RTC_MATCH_IRQ = 81, MICROCHIP_PFSOC_EMMC_SD_IRQ = 88, MICROCHIP_PFSOC_MMUART0_IRQ = 90, MICROCHIP_PFSOC_MMUART1_IRQ = 91, diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 3d1b3246db..36c894b677 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -183,6 +183,8 @@ static void microchip_pfsoc_soc_instance_init(Object *obj) object_initialize_child(obj, "sysreg", &s->sysreg, TYPE_MCHP_PFSOC_SYSREG); + object_initialize_child(obj, "rtc", &s->rtc, TYPE_MCHP_PFSOC_RTC); + object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy, TYPE_MCHP_PFSOC_DDR_SGMII_PHY); object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg, @@ -293,6 +295,15 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) memmap[MICROCHIP_PFSOC_PLIC].size); g_free(plic_hart_config); + /* RTC */ + sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, + memmap[MICROCHIP_PFSOC_RTC].base); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, + qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_RTC_WAKEUP_IRQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 1, + qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_RTC_MATCH_IRQ)); + /* DMA */ sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp); sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index b2b816de6a..877c020052 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -19,6 +19,7 @@ config MICROCHIP_PFSOC select MCHP_PFSOC_DMC select MCHP_PFSOC_IOSCB select MCHP_PFSOC_MMUART + select MCHP_PFSOC_RTC select MCHP_PFSOC_SYSREG select RISCV_ACLINT select SIFIVE_L2CC -- 2.53.0
