On Sun, Oct 04, 2026 at 01:02:13AM +0800, Bin Meng wrote: > With all previous changes, the Icicle Kit model is now able to boot > HSS v2024.06 through a Buildroot 2026.05 SD image to U-Boot and Linux. > > Document the tested source versions and exact commands to build HSS > and Buildroot. Include the sparse resize and GPT relocation steps > needed to make the generated SD image usable by QEMU. > > Explain the pinned firmware baseline and include the DDR pattern-test > patch used by the versioned test image. Document the tool check needed > for image-only builds and distinguish the DDR training failure from > the two investigated multi-hart startup races. Describe their visible > symptoms, affected source versions, and all three DTB supply paths. > > Also describe the RAM and serial setup, boot stages, and remaining > model limitations. The official HSS v2026.04.1 eNVM image was > also verified to reach the Linux login prompt with the same SD > image, while the functional test keeps its versioned baseline. > > Signed-off-by: Bin Meng <[email protected]> > > --- > > Changes in v3: > - Include the DDR pattern-test patch used by the functional-test image > - Document the image-only FPGA programming tool check > - Describe startup-race symptoms and link the firmware investigations > > docs/system/riscv/microchip-icicle-kit.rst | 130 ++++++++++++++++++++- > 1 file changed, 124 insertions(+), 6 deletions(-) > > diff --git a/docs/system/riscv/microchip-icicle-kit.rst > b/docs/system/riscv/microchip-icicle-kit.rst > index 138289a913..9fde3f1073 100644 > --- a/docs/system/riscv/microchip-icicle-kit.rst > +++ b/docs/system/riscv/microchip-icicle-kit.rst > @@ -19,12 +19,14 @@ The ``microchip-icicle-kit`` machine supports the > following devices: > * 4 U54 cores > * Core Level Interruptor (CLINT) > * Platform-Level Interrupt Controller (PLIC) > -* L2 Loosely Integrated Memory (L2-LIM) > +* L2 cache controller, including L2-LIM and L2-Zero windows > * DDR memory controller > +* System controller and system services mailbox > * 5 MMUARTs > * 1 DMA controller > * 2 GEM Ethernet controllers > * 1 SDHC storage controller > +* 1 Real-Time Clock > > The machine has a fixed 2 GiB of RAM. Other memory sizes are rejected. > The machine defaults to all five harts. ``-smp`` may select two to five > harts, > @@ -103,10 +105,126 @@ CAVEATS: > Running HSS > ----------- > > -The machine ``microchip-icicle-kit`` used to run the Hart Software Services > -(HSS_), however, the HSS development progressed and the QEMU machine > -implementation lacks behind. Currently, running the HSS no longer works. > -There is missing support in the clock and memory controller devices. In > -particular, reading from the SD card does not work. > +The ``microchip-icicle-kit`` machine can boot the Hart Software Services > +(HSS_), which then loads an HSS payload containing U-Boot from an SD card. > +The following flow was tested with HSS v2024.06 and Buildroot 2026.05.
As I said on the v2, I think this should be much more recent, I tried 2026.04 on top of your series and it seemed to work fine.
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