pmu.c can then be compiled once for system-mode alongside csr.c/csr.h in a follow up commit, since it's otherwise target agnostic.
Reviewed-by: Pierrick Bouvier <[email protected]> Signed-off-by: Anton Johansson <[email protected]> --- target/riscv/tcg/csr.h | 4 ++++ target/riscv/tcg/pmu.h | 3 --- target/riscv/tcg/pmu.c | 5 +++-- target/riscv/tcg/meson.build | 2 -- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/target/riscv/tcg/csr.h b/target/riscv/tcg/csr.h index 53ba3b4a4d..03f96cce04 100644 --- a/target/riscv/tcg/csr.h +++ b/target/riscv/tcg/csr.h @@ -99,4 +99,8 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index, target_ulong val); target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index); +/* Used in pmu.c */ +RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val, + bool upper_half, uint32_t ctr_idx); + #endif /* RISCV_CSR_H */ diff --git a/target/riscv/tcg/pmu.h b/target/riscv/tcg/pmu.h index fbdbfe7600..7e42359f87 100644 --- a/target/riscv/tcg/pmu.h +++ b/target/riscv/tcg/pmu.h @@ -21,7 +21,6 @@ #include "cpu.h" #include "qapi/error.h" -#include "exec/target_long.h" bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env, uint32_t target_ctr); @@ -38,7 +37,5 @@ int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, privilege_mode_t newpriv, bool new_virt); void riscv_pmu_decr_instret(CPURISCVState *env); -RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val, - bool upper_half, uint32_t ctr_idx); #endif /* RISCV_PMU_H */ diff --git a/target/riscv/tcg/pmu.c b/target/riscv/tcg/pmu.c index 1a4658319b..c8acb85df4 100644 --- a/target/riscv/tcg/pmu.c +++ b/target/riscv/tcg/pmu.c @@ -20,8 +20,9 @@ #include "qemu/log.h" #include "qemu/error-report.h" #include "qemu/timer.h" -#include "cpu.h" -#include "pmu.h" +#include "target/riscv/cpu.h" +#include "target/riscv/tcg/pmu.h" +#include "target/riscv/tcg/csr.h" #include "exec/icount.h" #include "system/device_tree.h" diff --git a/target/riscv/tcg/meson.build b/target/riscv/tcg/meson.build index a05ab642f4..954dfc10e0 100644 --- a/target/riscv/tcg/meson.build +++ b/target/riscv/tcg/meson.build @@ -25,5 +25,3 @@ riscv_system_ss.add(files( 'pmu.c', 'th_csr.c', )) - - -- 2.52.0
