Moves MAX and BARE cpus to separate typeinfo tables indexed by target_riscv64() during registration, similar to how ARM handles MAX cpu types.
Signed-off-by: Anton Johansson <[email protected]> --- target/riscv/cpu.c | 86 ++++++++++++++++++++++++++++++++---------------------- 1 file changed, 51 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cfc80aaaf1..d1727ce2f5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -3365,41 +3365,6 @@ static const TypeInfo riscv_cpu_type_infos[] = { ), DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_VENDOR_CPU, TYPE_RISCV_CPU), - DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_BARE_CPU, TYPE_RISCV_CPU, - /* - * Bare CPUs do not inherit the timer and performance - * counters from the parent class (see riscv_cpu_init() - * for info on why the parent enables them). - * - * Users have to explicitly enable these counters for - * bare CPUs. - */ - .bare = true, - - /* Set to QEMU's first supported priv version */ - .priv_spec = PRIV_VERSION_1_10_0, - - /* - * Support all available satp_mode settings. By default - * only MBARE will be available if the user doesn't enable - * a mode manually (see riscv_cpu_satp_mode_finalize()). - */ -#ifdef TARGET_RISCV32 - .cfg.max_satp_mode = VM_1_10_SV32, -#else - .cfg.max_satp_mode = VM_1_10_SV57, -#endif - ), - - DEFINE_RISCV_CPU(TYPE_RISCV_CPU_MAX, TYPE_RISCV_DYNAMIC_CPU, -#if defined(TARGET_RISCV32) - .misa_mxl_max = MXL_RV32, - .cfg.max_satp_mode = VM_1_10_SV32, -#elif defined(TARGET_RISCV64) - .misa_mxl_max = MXL_RV64, - .cfg.max_satp_mode = VM_1_10_SV57, -#endif - ), DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E, TYPE_RISCV_VENDOR_CPU, .misa_ext = RVI | RVM | RVA | RVC | RVU, @@ -3838,4 +3803,55 @@ static const TypeInfo riscv_cpu_type_infos[] = { DEFINE_RISCV64_PROFILE_CPU(TYPE_RISCV_CPU_RVA23S64, TYPE_RISCV_CPU_RV64I, RVA23S64), }; + +static const TypeInfo riscv_cpu_bare_type_infos[] = { + /* + * Bare CPUs do not inherit the timer and performance + * counters from the parent class (see riscv_cpu_init() + * for info on why the parent enables them). + * + * Users have to explicitly enable these counters for + * bare CPUs. + * + * Support all available satp_mode settings. By default + * only MBARE will be available if the user doesn't enable + * a mode manually (see riscv_cpu_satp_mode_finalize()). + */ + + /* 32-bit entry */ + DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_BARE_CPU, TYPE_RISCV_CPU, + /* Set to QEMU's first supported priv version */ + .priv_spec = PRIV_VERSION_1_10_0, + .bare = true, + .cfg.max_satp_mode = VM_1_10_SV32, + ), + /* 64-bit entry */ + DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_BARE_CPU, TYPE_RISCV_CPU, + /* Set to QEMU's first supported priv version */ + .priv_spec = PRIV_VERSION_1_10_0, + .bare = true, + .cfg.max_satp_mode = VM_1_10_SV57, + ), +}; + +static const TypeInfo riscv_cpu_max_type_infos[2] = { + /* 32-bit entry */ + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_MAX, TYPE_RISCV_DYNAMIC_CPU, + .misa_mxl_max = MXL_RV32, + .cfg.max_satp_mode = VM_1_10_SV32, + ), + /* 64-bit entry */ + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_MAX, TYPE_RISCV_DYNAMIC_CPU, + .misa_mxl_max = MXL_RV64, + .cfg.max_satp_mode = VM_1_10_SV57, + ), +}; + +static void riscv_register_max_bare_types(void) +{ + bool rv64 = target_riscv64(); + type_register_static(&riscv_cpu_bare_type_infos[rv64]); + type_register_static(&riscv_cpu_max_type_infos[rv64]); +} +type_init(riscv_register_max_bare_types) DEFINE_TYPES(riscv_cpu_type_infos) -- 2.52.0
