[PATCH 02/10] target/mips/gdbstub: Reduce to a single gdb_get_regl() call

[Philippe Mathieu-Daudé]

Store the register value in a local @val in each switch case,
then append it once at the end of mips_cpu_gdb_read_register().

No functional change.

Signed-off-by: Philippe Mathieu-Daudé <phi...@oss.qualcomm.com>
---
 target/mips/gdbstub.c | 76 ++++++++++++++++++++++++-------------------
 1 file changed, 43 insertions(+), 33 deletions(-)

diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c
index 8e0b08a096c..7598aab6158 100644
--- a/target/mips/gdbstub.c
+++ b/target/mips/gdbstub.c
@@ -27,6 +27,7 @@
 int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
 {
     CPUMIPSState *env = cpu_env(cs);
+    uint64_t val;
 
     if (n < 32) {
         return gdb_get_regl(mem_buf, env->active_tc.gpr[n]);
@@ -34,46 +35,55 @@ int mips_cpu_gdb_read_register(CPUState *cs, GByteArray 
*mem_buf, int n)
     if (env->CP0_Config1 & (1 << CP0C1_FP) && n >= 38 && n < 72) {
         switch (n) {
         case 70:
-            return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr31);
+            val = (int32_t)env->active_fpu.fcr31;
+            break;
         case 71:
-            return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr0);
+            val = (int32_t)env->active_fpu.fcr0;
+            break;
         default:
             if (env->CP0_Status & (1 << CP0St_FR)) {
-                return gdb_get_regl(mem_buf,
-                    env->active_fpu.fpr[n - 38].d);
+                val = env->active_fpu.fpr[n - 38].d;
             } else {
-                return gdb_get_regl(mem_buf,
-                    env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
+                val = env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX];
             }
+            break;
+        }
+    } else {
+        switch (n) {
+        case 32:
+            val = (int32_t)env->CP0_Status;
+            break;
+        case 33:
+            val = env->active_tc.LO[0];
+            break;
+        case 34:
+            val = env->active_tc.HI[0];
+            break;
+        case 35:
+            val = env->CP0_BadVAddr;
+            break;
+        case 36:
+            val = (int32_t)env->CP0_Cause;
+            break;
+        case 37:
+            val = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
+            break;
+        case 72:
+            val = 0; /* fp */
+            break;
+        case 89:
+            val = (int32_t)env->CP0_PRid;
+            break;
+        default:
+            if (n > 89) {
+                return 0;
+            }
+            /* 16 embedded regs.  */
+            val = 0;
+            break;
         }
     }
-    switch (n) {
-    case 32:
-        return gdb_get_regl(mem_buf, (int32_t)env->CP0_Status);
-    case 33:
-        return gdb_get_regl(mem_buf, env->active_tc.LO[0]);
-    case 34:
-        return gdb_get_regl(mem_buf, env->active_tc.HI[0]);
-    case 35:
-        return gdb_get_regl(mem_buf, env->CP0_BadVAddr);
-    case 36:
-        return gdb_get_regl(mem_buf, (int32_t)env->CP0_Cause);
-    case 37:
-        return gdb_get_regl(mem_buf, env->active_tc.PC |
-                                     !!(env->hflags & MIPS_HFLAG_M16));
-    case 72:
-        return gdb_get_regl(mem_buf, 0); /* fp */
-    case 89:
-        return gdb_get_regl(mem_buf, (int32_t)env->CP0_PRid);
-    default:
-        if (n > 89) {
-            return 0;
-        }
-        /* 16 embedded regs.  */
-        return gdb_get_regl(mem_buf, 0);
-    }
-
-    return 0;
+    return gdb_get_regl(mem_buf, val);
 }
 
 int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
-- 
2.55.0