Move the MXL-based selection of the register width out of riscv_cpu_gdb_read_register() into a helper, so it can be reused by the following patch.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]> --- target/riscv/gdbstub.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 9abbf5bcdf0..b3c11db5397 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -54,9 +54,25 @@ static uint64_t ldn(CPURISCVState *env, uint8_t *mem_buf, size_t regsz) return (mo_endian_env(env) == MO_LE ? ldn_le_p : ldn_be_p)(mem_buf, regsz); } -int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) +static int riscv_gdb_get_reg_mxl(CPUState *cs, + GByteArray *buf, uint64_t val) { RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs); + + switch (mcc->def->misa_mxl_max) { + case MXL_RV32: + return gdb_get_reg32(buf, val); + case MXL_RV64: + case MXL_RV128: + return gdb_get_reg64(buf, val); + default: + g_assert_not_reached(); + } + return 0; +} + +int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) +{ RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; uint64_t tmp; @@ -69,16 +85,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) return 0; } - switch (mcc->def->misa_mxl_max) { - case MXL_RV32: - return gdb_get_reg32(mem_buf, tmp); - case MXL_RV64: - case MXL_RV128: - return gdb_get_reg64(mem_buf, tmp); - default: - g_assert_not_reached(); - } - return 0; + return riscv_gdb_get_reg_mxl(cs, mem_buf, tmp); } int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) -- 2.55.0
