Add a mips_env_is_64bit() helper and inline gdb_get_regl() as mips_gdb_get_regl(), so that the GDB register size follows the emulated CPU model rather than the target build's TARGET_LONG_BITS.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]> --- target/mips/internal.h | 5 +++++ target/mips/gdbstub.c | 11 +++++++++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 7dba22300b1..0c9b1335ebb 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -228,6 +228,11 @@ static inline void mips_env_set_pc(CPUMIPSState *env, target_ulong value) } } +static inline bool mips_env_is_64bit(const CPUMIPSState *env) +{ + return env->cpu_model->insn_flags & CPU_MIPS64; +} + static inline bool mips_env_is_bigendian(CPUMIPSState *env) { return extract32(env->CP0_Config0, CP0C0_BE, 1); diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c index 7598aab6158..78d3e9a5b9b 100644 --- a/target/mips/gdbstub.c +++ b/target/mips/gdbstub.c @@ -24,13 +24,20 @@ #include "gdbstub/helpers.h" #include "fpu_helper.h" +static int mips_gdb_get_regl(const CPUMIPSState *env, + GByteArray *buf, uint64_t val) +{ + return mips_env_is_64bit(env) ? gdb_get_reg64(buf, val) + : gdb_get_reg32(buf, val); +} + int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { CPUMIPSState *env = cpu_env(cs); uint64_t val; if (n < 32) { - return gdb_get_regl(mem_buf, env->active_tc.gpr[n]); + return mips_gdb_get_regl(env, mem_buf, env->active_tc.gpr[n]); } if (env->CP0_Config1 & (1 << CP0C1_FP) && n >= 38 && n < 72) { switch (n) { @@ -83,7 +90,7 @@ int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) break; } } - return gdb_get_regl(mem_buf, val); + return mips_gdb_get_regl(env, mem_buf, val); } int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) -- 2.55.0
