The GIC cpu interface has a set of GIC LDnnn insns which behave exactly like the GIC CDnnn ones except that they always operate on the logical interrupt domain. (EL3 can use these to examine and update the state of the interrupts in the physical interrupt domain for lower exception levels.)
We won't need these until we implement EL3 support, but since we've put in all the necessary groundwork for the reginfo structs to just work, we might as well add them now. The writefns will select the domain to use based on the opc1 field. As with VD, there is no LD insn for CDIA, CDNMIA or CDEOI. Signed-off-by: Peter Maydell <[email protected]> --- target/arm/tcg/gicv5-cpuif.c | 40 ++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 64e59589cc7..69e51359f22 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -1501,6 +1501,46 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = { .accessfn = access_gicv5_ich_reg, .writefn = gic_cdhm_write, }, + { .name = "GIC_LDDIS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 6, .crn = 12, .crm = 1, .opc2 = 0, + .access = PL3_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .writefn = gic_cddis_write, + }, + { .name = "GIC_LDEN", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 6, .crn = 12, .crm = 1, .opc2 = 1, + .access = PL3_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .writefn = gic_cden_write, + }, + { .name = "GIC_LDPRI", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 6, .crn = 12, .crm = 1, .opc2 = 2, + .access = PL3_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .writefn = gic_cdpri_write, + }, + { .name = "GIC_LDAFF", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 6, .crn = 12, .crm = 1, .opc2 = 3, + .access = PL3_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .writefn = gic_cdaff_write, + }, + { .name = "GIC_LDPEND", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 6, .crn = 12, .crm = 1, .opc2 = 4, + .access = PL3_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .writefn = gic_cdpend_write, + }, + { .name = "GIC_LDRCFG", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 6, .crn = 12, .crm = 1, .opc2 = 5, + .access = PL3_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .writefn = gic_cdrcfg_write, + }, + { .name = "GIC_LDDI", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 6, .crn = 12, .crm = 2, .opc2 = 0, + .access = PL3_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .writefn = gic_cddi_write, + }, + { .name = "GIC_LDHM", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 6, .crn = 12, .crm = 2, .opc2 = 1, + .access = PL3_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .writefn = gic_cdhm_write, + }, { .name = "ICC_IDR0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, -- 2.43.0
