Implement the redirection of ICC_PPI_CACTIVER<n>_EL1 and ICC_PPI_SACTIVER<n>_EL1 to the virtual ICV_ versions of these registers. The underlying state here is held in ICH_PPI_ACTIVER<n>_EL2, but the inner-guest facing view has set/clear semantics.
Signed-off-by: Peter Maydell <[email protected]> --- target/arm/tcg/gicv5-cpuif.c | 38 ++++++++++++++++++++++++++++++------ 1 file changed, 32 insertions(+), 6 deletions(-) diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index b55fe4991ba..876f5813d5a 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -442,20 +442,42 @@ static uint64_t gic_ppi_hmr_read(CPUARMState *env, const ARMCPRegInfo *ri) return value; } +static uint64_t gic_ppi_active_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + if (gicv5_icv_access(env)) { + uint64_t value = env->gicv5_cpuif.ich_ppi_active[ri->opc2 & 1]; + + value &= ~env->gicv5_cpuif.ich_ppi_hvi[ri->opc2 & 1]; + return value; + } else { + return raw_read(env, ri); + } +} + static void gic_ppi_cactive_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - uint64_t old = raw_read(env, ri); - raw_write(env, ri, old & ~value); - gic_recalc_ppi_hppi(env); + if (gicv5_icv_access(env)) { + value &= ~env->gicv5_cpuif.ich_ppi_hvi[ri->opc2 & 1]; + env->gicv5_cpuif.ich_ppi_active[ri->opc2 & 1] &= ~value; + } else { + uint64_t old = raw_read(env, ri); + raw_write(env, ri, old & ~value); + gic_recalc_ppi_hppi(env); + } } static void gic_ppi_sactive_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - uint64_t old = raw_read(env, ri); - raw_write(env, ri, old | value); - gic_recalc_ppi_hppi(env); + if (gicv5_icv_access(env)) { + value &= ~env->gicv5_cpuif.ich_ppi_hvi[ri->opc2 & 1]; + env->gicv5_cpuif.ich_ppi_active[ri->opc2 & 1] |= value; + } else { + uint64_t old = raw_read(env, ri); + raw_write(env, ri, old | value); + gic_recalc_ppi_hppi(env); + } } static void gic_ppi_cpend_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1043,6 +1065,7 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = { .access = PL1_RW, .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, .fgt = FGT_ICC_PPI_ACTIVERN_EL1, .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_active[0]), + .readfn = gic_ppi_active_read, .writefn = gic_ppi_cactive_write, }, { .name = "ICC_PPI_CACTIVER1_EL1", .state = ARM_CP_STATE_AA64, @@ -1050,6 +1073,7 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = { .access = PL1_RW, .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, .fgt = FGT_ICC_PPI_ACTIVERN_EL1, .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_active[1]), + .readfn = gic_ppi_active_read, .writefn = gic_ppi_cactive_write, }, { .name = "ICC_PPI_SACTIVER0_EL1", .state = ARM_CP_STATE_AA64, @@ -1057,6 +1081,7 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = { .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, .fgt = FGT_ICC_PPI_ACTIVERN_EL1, .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_active[0]), + .readfn = gic_ppi_active_read, .writefn = gic_ppi_sactive_write, }, { .name = "ICC_PPI_SACTIVER1_EL1", .state = ARM_CP_STATE_AA64, @@ -1064,6 +1089,7 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = { .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, .fgt = FGT_ICC_PPI_ACTIVERN_EL1, .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_active[1]), + .readfn = gic_ppi_active_read, .writefn = gic_ppi_sactive_write, }, { .name = "ICC_PPI_HMR0_EL1", .state = ARM_CP_STATE_AA64, -- 2.43.0
