Implement ICH_PPI_DVIR<n>_EL2, which is the register that controls whether pending physical PPIs are directly injected as virtual PPIs to the virtual interrupt domain.
Bits in this register are RAZ/WI from EL1 and EL2 if the PPI is not assigned to the current interrupt domain, but since we don't yet implement EL3 GICv5 support yet all PPIs are always assigned to the current interrupt domain. In this commit we just implement the register access to the state; actual injection of PPIs will be dealt with later. We give the register a writefn because eventually writing to this will need to trigger a recalculation of VIRQ/VFIQ. Signed-off-by: Peter Maydell <[email protected]> --- target/arm/cpu.h | 1 + target/arm/tcg/gicv5-cpuif.c | 27 +++++++++++++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 287cfa87140..5d3587739d7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -599,6 +599,7 @@ typedef struct CPUArchState { uint64_t ich_ppi_active[GICV5_NUM_PPIS / 64]; uint64_t ich_ppi_pend[GICV5_NUM_PPIS / 64]; uint64_t ich_ppi_enable[GICV5_NUM_PPIS / 64]; + uint64_t ich_ppi_dvi[GICV5_NUM_PPIS / 64]; uint64_t ich_ppi_priority[GICV5_NUM_PPIS / 8]; } gicv5_cpuif; diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index b901e64ef0d..2141f1d8e2c 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -487,6 +487,12 @@ static void gic_ich_ppi_priority_write(CPUARMState *env, const ARMCPRegInfo *ri, raw_write(env, ri, value); } +static void gic_ich_ppi_dvi_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + raw_write(env, ri, value); +} + /* * ICC_APR_EL1 is banked and reads/writes as the version for the * current logical interrupt domain. @@ -961,6 +967,27 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = { .accessfn = access_gicv5_ich_reg, .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ich_apr_el2), }, + /* + * Note that DVIR bits RAZ/WI when the PPI isn't assigned to the + * current domain, so we will need to mask them when we implement + * EL3 support and ICC_PPI_DOMAINR<n>_EL3 + */ + { .name = "ICH_PPI_DVIR0_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 10, .opc2 = 0, + .access = PL2_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset = 0xb40, + .accessfn = access_gicv5_ich_reg, + .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ich_ppi_dvi[0]), + .writefn = gic_ich_ppi_dvi_write, + }, + { .name = "ICH_PPI_DVIR1_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 10, .opc2 = 1, + .access = PL2_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset = 0xb48, + .accessfn = access_gicv5_ich_reg, + .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ich_ppi_dvi[1]), + .writefn = gic_ich_ppi_dvi_write, + }, { .name = "ICH_PPI_ENABLER0_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 10, .opc2 = 2, .access = PL2_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, -- 2.43.0
