irs_map_l2_istr_write() makes the L2 IST for a specified interrupt valid by finding the L1 ISTE and setting its valid bit. For virtualization, we want to do something similar for the ISTs used for virtual LPIs and SPIs. Factor out the "do the work" part of the function from the specifics of the IRS_MAP_L2_ISTR register.
Signed-off-by: Peter Maydell <[email protected]> --- hw/intc/arm_gicv5.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 1d6f2767d02..3fac52012b1 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -1096,11 +1096,8 @@ static void initialize_ist_config(GICv5Common *cs, GICv5Domain domain, cfg->valid = true; } -static void irs_map_l2_istr_write(GICv5 *s, GICv5Domain domain, uint64_t value) +static void map_l2_istr(GICv5Common *cs, GICv5ISTConfig *cfg, uint32_t intid) { - GICv5Common *cs = ARM_GICV5_COMMON(s); - GICv5ISTConfig *cfg = &s->phys_lpi_config[domain]; - uint32_t intid = FIELD_EX32(value, IRS_MAP_L2_ISTR, ID); hwaddr l1_addr; uint64_t l1_iste; MemTxResult res; @@ -1138,6 +1135,15 @@ txfail: "physical address 0x" HWADDR_FMT_plx "\n", intid, l1_addr); } +static void irs_map_l2_istr_write(GICv5 *s, GICv5Domain domain, uint64_t value) +{ + GICv5Common *cs = ARM_GICV5_COMMON(s); + GICv5ISTConfig *cfg = &s->phys_lpi_config[domain]; + uint32_t intid = FIELD_EX32(value, IRS_MAP_L2_ISTR, ID); + + map_l2_istr(cs, cfg, intid); +} + bool gicv5_set_resident(GICv5Common *cs, GICv5Domain domain, bool valid, uint32_t vpeid, bool db, uint8_t dbpm, uint32_t vmid, uint32_t cpuidx) -- 2.43.0
