The GIC cpu interface has a set of GIC VDnnn insns which behave exactly like the GIC CDnnn ones except that they always operate on the virtual interrupt domain. (EL2 can use these to examine and update the state of the interrupts of its guest.)
Now we've updated the writefns to handle the virtual interrupt domain by looking at the opc1 field, we can implement these using the existing writefns. Note that there is no VD insn for CDIA, CDNMIA or CDEOI. Signed-off-by: Peter Maydell <[email protected]> --- target/arm/tcg/gicv5-cpuif.c | 48 ++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 7f0109e9b12..64e59589cc7 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -1453,6 +1453,54 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = { .fgt = FGT_GICRCDNMIA, .readfn = gicr_cdia_read, }, + { .name = "GIC_VDDIS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 0, + .access = PL2_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .accessfn = access_gicv5_ich_reg, + .writefn = gic_cddis_write, + }, + { .name = "GIC_VDEN", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1, + .access = PL2_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .accessfn = access_gicv5_ich_reg, + .writefn = gic_cden_write, + }, + { .name = "GIC_VDPRI", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 2, + .access = PL2_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .accessfn = access_gicv5_ich_reg, + .writefn = gic_cdpri_write, + }, + { .name = "GIC_VDAFF", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 3, + .access = PL2_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .accessfn = access_gicv5_ich_reg, + .writefn = gic_cdaff_write, + }, + { .name = "GIC_VDPEND", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 4, + .access = PL2_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .accessfn = access_gicv5_ich_reg, + .writefn = gic_cdpend_write, + }, + { .name = "GIC_VDRCFG", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 5, + .access = PL2_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .accessfn = access_gicv5_ich_reg, + .writefn = gic_cdrcfg_write, + }, + { .name = "GIC_VDDI", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 12, .crm = 2, .opc2 = 0, + .access = PL2_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .accessfn = access_gicv5_ich_reg, + .writefn = gic_cddi_write, + }, + { .name = "GIC_VDHM", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 12, .crm = 2, .opc2 = 1, + .access = PL2_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .accessfn = access_gicv5_ich_reg, + .writefn = gic_cdhm_write, + }, { .name = "ICC_IDR0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, -- 2.43.0
