Re: [PATCH 68/86] hw/intc/arm_gicv5: Implement gicv5_set_resident()

[Philippe Mathieu-Daudé]

On 13/10/26 10:39, Peter Maydell wrote:

When the GICv5 CPU interface wants to make a VPE resident, it calls
gicv5_set_resident(). Currently that is a do-nothing placeholder;
implement the required behaviour of tracking on the IRS side that
the VPE is resident on this CPU, and remembering the information
about the doorbell interrupt.

For each CPU, we keep a note of the current VPE that is resident (if
any), so we have an easy way to get to that information given the CPU
index in functions like gicv5_set_priority().  Since the only way to
make a VPE invalid is to make the entire VM invalid, we only need to
set this info in gicv5_set_resident() and then clear it when a VM
becomes invalid or the whole VM table is made invalid.

Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
---
  hw/intc/arm_gicv5.c         | 115 +++++++++++++++++++++++++++++++++++-
  hw/intc/trace-events        |   2 +
  include/hw/intc/arm_gicv5.h |   5 ++

(please enable scripts/git.orderfile to ease mailing list code review)

@@ -1566,6 +1649,8 @@ static void irs_vmt_baser_write(GICv5 *s, GICv5Domain 
domain, uint64_t value)
              return;
          }
          irs_clean_vm_cache(cs, &s->vmt_config[domain]);
+        /* No VPE is now resident on any CPU */
+        memset(s->res_vpe, 0, sizeof(VPE) * cs->num_cpus);

res_vpe is declared as:

  VPE **res_vpe;

so IIUC we should use sizeof(*VPE), or the sizeof(*s->res_vpe)
used below to keep the same style.

          cs->irs_vmt_baser[domain] = FIELD_DP64(cs->irs_vmt_baser[domain],
                                                 IRS_VMT_BASER, VALID, valid);

@@ -2884,6 +2985,11 @@ static void gicv5_reset_hold(Object *obj, ResetType type)
              g_hash_table_remove_all(s->vmt_config[i].vm_cache);
          }
      }
+
+    if (s->res_vpe) {
+        /* No VPE is now resident on any CPU */
+        memset(s->res_vpe, 0, sizeof(*s->res_vpe) * cs->num_cpus);

OK.

+    }
  }

static void gicv5_set_idregs(GICv5Common *cs)

@@ -2988,6 +3094,10 @@ static void gicv5_realize(DeviceState *dev, Error **errp)
              s->hppi[i] = g_new0(GICv5PendingIrq, cs->num_cpus);
          }
      }
+
+    if (cs->has_virt) {
+        s->res_vpe = g_new0(VPE *, cs->num_cpus);

OK.

+    }
  }

diff --git a/include/hw/intc/arm_gicv5.h b/include/hw/intc/arm_gicv5.h
index 28417317376..ac85cad3eb5 100644
--- a/include/hw/intc/arm_gicv5.h
+++ b/include/hw/intc/arm_gicv5.h
@@ -40,6 +40,8 @@ typedef struct GICv5VMTConfig {
      GHashTable *vm_cache;
  } GICv5VMTConfig;

+typedef struct VPE VPE;

+
  /*
   * This class is for TCG-specific state for the GICv5.
   */
@@ -53,6 +55,9 @@ struct GICv5 {

/* We cache the HPPI for each CPU for each domain here */

      GICv5PendingIrq *hppi[NUM_GICV5_DOMAINS];
+
+    /* Array: for each CPU, either NULL or ptr to the resident VPE */
+    VPE **res_vpe;
  };

struct GICv5Class {