When FEAT_GCIE and FEAT_EL2 are implemented, the GICv5 specification requires that the old GICv3 ICC_SRE_EL1 and ICC_SRE_EL2 registers are present, with RAO/WI bits, even if FEAT_GCIE_LEGACY is not implemented or enabled. ICC_SRE_EL3 is not present, but the CPU behaves as if its Enable and SRE bits are always set. (See R_SLVXV, R_MCTMX, R_HQBBN.)
Implement the ICC_SRE_EL1 and ICC_SRE_EL2 registers. For QEMU, this "all bits RAO" is identical to how we implemented it for GICv3, because we didn't implement the memory-map register interface, we didn't support IRQ or FIQ bypass and we took advantage of the IMPDEF option to make the ENABLE bit RAO so we didn't need to trap lower-EL accesses to ICC_SRE_ELx. The RAO behaviours correspond to "do nothing" -- don't trap system register accesses, no IRQ/FIQ bypass handling -- so we don't need any special handling in any part of the CPU implementation, just as we didn't for GICv3. Because ICC_SRE_EL1 is EL1-visible but only present when FEAT_EL2 is implemented, we need to put it in a cpreg array that we only register when ARM_FEATURE_EL2 is set, rather than being able to list it in the main gicv5_cpuif_reginfo array and relying on the access field as we do for other FEAT_EL2 GICv5 registers. Signed-off-by: Peter Maydell <[email protected]> --- target/arm/tcg/gicv5-cpuif.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index be34312d242..8cb790204f1 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -1017,6 +1017,11 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = { .fieldoffset = offsetof(CPUARMState, cp15.fgt_read[FGTREG_ICH_HFGRTR]), .resetvalue = ICH_HFGRTR_EL2_RES1_MASK, }, + { .name = "ICC_SRE_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 9, .opc2 = 5, + .access = PL2_RW, .type = ARM_CP_NO_RAW | ARM_CP_CONST, + .resetvalue = 0xf, + }, { .name = "ICH_HFGWTR_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 9, .opc2 = 6, .access = PL2_RW, .type = ARM_CP_NO_RAW, @@ -1116,6 +1121,14 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = { }, }; +static const ARMCPRegInfo gicv5_cpuif_el2_reginfo[] = { + { .name = "ICC_SRE_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 5, + .access = PL1_RW, .type = ARM_CP_NO_RAW | ARM_CP_CONST, + .resetvalue = 0x7, + }, +}; + void define_gicv5_cpuif_regs(ARMCPU *cpu) { if (cpu_isar_feature(aa64_gcie, cpu)) { @@ -1153,5 +1166,9 @@ void define_gicv5_cpuif_regs(ARMCPU *cpu) }; define_one_arm_cp_reg(cpu, &ppi_prio); } + + if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { + define_arm_cp_regs(cpu, gicv5_cpuif_el2_reginfo); + } } } -- 2.43.0
