Implement the ICH_VCTLR_EL2 and ICH_VMCR_EL2 registers, which hold hypervisor state for controlling its guest's GICv5 virtual cpu interface.
We give these write functions and mark them as ARM_CP_IO even though they currently don't do anything special on write, because later on we will need changes to fields in these registers to trigger a recalculation of whether the VIRQ and VFIQ interrupts are signalled. Signed-off-by: Peter Maydell <[email protected]> --- target/arm/cpu.h | 2 ++ target/arm/tcg/gicv5-cpuif.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5d3587739d7..4e7076a5339 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -596,6 +596,8 @@ typedef struct CPUArchState { GICv5PendingIrq ppi_hppi[NUM_GICV5_DOMAINS]; uint64_t ich_apr_el2; + uint64_t ich_vctlr_el2; + uint64_t ich_vmcr_el2; uint64_t ich_ppi_active[GICV5_NUM_PPIS / 64]; uint64_t ich_ppi_pend[GICV5_NUM_PPIS / 64]; uint64_t ich_ppi_enable[GICV5_NUM_PPIS / 64]; diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 2141f1d8e2c..ac667c84c2f 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -493,6 +493,18 @@ static void gic_ich_ppi_dvi_write(CPUARMState *env, const ARMCPRegInfo *ri, raw_write(env, ri, value); } +static void gic_ich_vctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + raw_write(env, ri, value); +} + +static void gic_ich_vmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + raw_write(env, ri, value); +} + /* * ICC_APR_EL1 is banked and reads/writes as the version for the * current logical interrupt domain. @@ -1034,6 +1046,22 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = { .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ich_ppi_active[1]), .writefn = gic_ich_ppi_active_write, }, + { .name = "ICH_VCTLR_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 11, .opc2 = 4, + .access = PL2_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset = 0xb28, + .accessfn = access_gicv5_ich_reg, + .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ich_vctlr_el2), + .writefn = gic_ich_vctlr_write, + }, + { .name = "ICH_VMCR_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 11, .opc2 = 7, + .access = PL2_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset = 0x4c8, + .accessfn = access_gicv5_ich_reg, + .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ich_vmcr_el2), + .writefn = gic_ich_vmcr_write, + }, }; void define_gicv5_cpuif_regs(ARMCPU *cpu) -- 2.43.0
