Hi Philippe, thanks again for reviewing. On Tue, 2026-10-20 at 21:30 +0200, Philippe Mathieu-Daudé wrote: > > > Could we add tests (in tests/tcg, following commit 57b484e2d23 > "target/riscv: fix RV32 fixed counter accesses" which uses the > debian-all-test-cross image -- where gcc-sparc64-linux-gnu is > available)? Actually we could put them in tests/tcg/multiarch/ > as generic AES tests. >
Sure. I'll start working on tests after fixing other stuff that comes
up during initial review.
> >
> > +/*
> > + * SPARC four-operand AES round (Section 7.3).
> > + * s2:s3 holds the state in big-endian order; half selects output
> > columns
> > + * 0-1 or 2-3, and key supplies their round key. dec selects
> > decryption;
> > + * last omits MixColumns/InvMixColumns. Return the selected 64-
> > bit half.
>
> Please document the non-obvious invariant:
>
> * Note all 64-bit values (state and key) hold AES bytes in big-
> endian
> * order, i.e. the most significant byte is the first state byte.
Noted for v2.
>
> > + */
> > +static uint64_t aes_round(uint64_t key, uint64_t s2, uint64_t s3,
> > + int half, bool dec, bool last)
> > +{
> > + AESState st, rk = { 0 }, r;
> > + const unsigned first = HOST_BIG_ENDIAN ? 0 : 1;
> > + const unsigned out = first ^ half;
> > +
> > + st.d[first] = s2; /* columns 0-1 */
> > + st.d[first ^ 1] = s3; /* columns 2-3 */
> > + rk.d[out] = key;
>
> Nitpicking, maybe zero the other half explicitly here instead of { 0
> }:
>
> rk.d[out ^ 1] = 0;
Noted for v2.
/Stian
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