From: Alistair Francis <[email protected]> The following changes since commit d73149283205645625bfa9fe029cfb68e4c4a9ae:
Merge tag 'samuel-thibault' of https://people.debian.org/~sthibault/qemu into staging (2026-10-24 16:09:37 +0200) are available in the Git repository at: https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20261027 for you to fetch changes up to bf67d56f282c1ee25b67dfda3f8ca54d2bd4648e: target/riscv: Fix CPU state access on big-endian hosts (2026-10-27 10:26:46 +1000) ---------------------------------------------------------------- RISC-V PR for 11.2 * Add experimental Zvabd extension support * Mask vsepc according to IALIGN * Reset vCPU on VM reset via MP_STATE_INIT_RECEIVED * Improve modeling of the Atlantis UART * Fix IOMMU entry leak with ioatc-limit=0 * Fix integer handling issues in k230_gsdma and k230_decomp_gzip * Reclaim invalidated IOATC entries for IOMMU * Duct tape fix for QMP and RV profiles introspection * Move RISC-V 'Z' CPU properties section to removed features * Use TSO barriers instead of full barriers for Ztso * Make mnstatus.MNPELP writable with Zicfilp * Gate envcfg CBO fields on extensions * Fix stale PMP state across reset * Use 1ULL for a value we're going to shift by 63 * Remove unused IMISC macro * Encode debug translation ranges in IOMMU * Allow regular mstatus MPV/GVA writes again * Fix uninitialised upper half in pmu_timer_trigger_irq * Fix CPU state access on big-endian hosts ---------------------------------------------------------------- Anton Johansson (1): target/riscv: Fix CPU state access on big-endian hosts Daniel Henrique Barboza (3): target/riscv/cpu.c: duct tape fix for QMP + RV profiles introspection include/hw/intc/riscv_imsic.h: remove unused macro target/riscv/csr.c: allow regular mstatus MPV/GVA writes again Harshit Mukhedkar (1): target/riscv: fix uninitialised upper half in pmu_timer_trigger_irq() Mingliang Liu (2): disas/riscv: Support vabs.v pseudo-instruction tests/tcg/riscv64: Add Zvabd extension tests Peter Maydell (1): target/riscv: Use 1ULL for a value we're going to shift by 63 Philippe Mathieu-Daudé (1): docs: Move RISC-V 'Z' CPU properties section to removed features Portia Stephens (3): hw/riscv/atlantis: Use dw8250 UART model hw/riscv/atlantis: Add all UARTs for Atlantis SoC docs/atlantis: Update Atlantis UART documentation Rick Richard (1): target/riscv: Use TSO barriers instead of full barriers for Ztso Sebastian Alba Vives (2): target/riscv: pmp: clear A and L on every implemented PMP entry at reset target/riscv: pmp: reset the derived PMP bounds and rule count Tan Chi (3): hw/riscv/riscv-iommu: fix entry leak with ioatc-limit=0 hw/riscv/riscv-iommu: serialize IOATC accesses hw/riscv/riscv-iommu: reclaim invalidated IOATC entries Tao Ding (5): hw/misc: fix calculating output address overflow in k230_decomp_gzip hw/misc: fix calculating input address overflow in k230_decomp_gzip hw/misc: use hwaddr for the k230_decomp_gzip input address qtest: fix k230_decomp_gzip test integer handling issues hw/dma: fix k230_gsdma integer handling issues Wang Yechao (1): target/riscv/kvm: Reset vCPU on VM reset via MP_STATE_INIT_RECEIVED Zephyr Li (2): target/riscv: mask vsepc according to IALIGN hw/riscv/riscv-iommu: encode debug translation ranges Zhibo Hong (1): target/riscv: Add support for the Zvabd extension wangyang (2): target/riscv: make mnstatus.MNPELP writable with Zicfilp target/riscv: gate envcfg CBO fields on extensions docs/about/deprecated.rst | 24 - docs/about/removed-features.rst | 7 + docs/system/riscv/tt_atlantis.rst | 7 +- hw/riscv/riscv-iommu.h | 1 + include/hw/intc/riscv_imsic.h | 1 - include/hw/riscv/tt_atlantis.h | 13 +- target/riscv/helper.h | 26 ++ target/riscv/cpu_cfg_fields.h.inc | 1 + target/riscv/insn32.decode | 10 + disas/riscv.c | 14 + hw/dma/k230_gsdma.c | 84 ++-- hw/misc/k230_decomp_gzip.c | 6 +- hw/riscv/riscv-iommu.c | 190 ++++---- hw/riscv/tt_atlantis.c | 68 +-- target/riscv/cpu.c | 22 +- target/riscv/kvm/kvm-cpu.c | 27 ++ target/riscv/tcg/csr.c | 50 ++- target/riscv/tcg/pmp.c | 10 +- target/riscv/tcg/pmu.c | 18 +- target/riscv/tcg/tcg-cpu.c | 6 + target/riscv/tcg/translate.c | 32 +- target/riscv/tcg/vector_helper.c | 56 +++ tests/qtest/iommu-riscv-test.c | 193 ++++++++ tests/qtest/k230-decomp-gzip-test.c | 2 +- disas/riscv-op.c.inc | 9 + target/riscv/tcg/insn_trans/trans_rvi.c.inc | 4 +- target/riscv/tcg/insn_trans/trans_rvv.c.inc | 49 ++- hw/riscv/Kconfig | 2 +- tests/tcg/riscv64/system/meson.build | 12 + tests/tcg/riscv64/test-vsepc-masking.S | 54 +++ tests/tcg/riscv64/test-zvabd.S | 659 ++++++++++++++++++++++++++++ 31 files changed, 1423 insertions(+), 234 deletions(-) create mode 100644 tests/tcg/riscv64/test-vsepc-masking.S create mode 100644 tests/tcg/riscv64/test-zvabd.S
