The riscv64 backend mishandles constant operands of RVV .vi forms: - logical ops apply the immediate at a stale SEW (wrong results, since v9.2); - arithmetic, compare and select ops encode the whole replicated 64-bit constant instead of one element; - shifts take uimm5, but the encoder checks for simm5.
1-2: add a uimm5 encoder for shifts, 3-4: extract one element (vec_imm()) for arithmetic and compare/select, 5: follow rth suggestion of adding a new constraint to pick the smallest element size at which the constant replicates as a simm5, and the emitter switches SEW to it, 6: AI-generated regression test. Tested with qemu-aarch64 built for a riscv64 host (debug-TCG), run under qemu-riscv64 -cpu max: the new test fails or aborts before the series, and passes with it at every SVE vector length. [1] https://lore.kernel.org/qemu-devel/[email protected]/ Supersedes: <[email protected]> Philippe Mathieu-Daudé (6): tcg/riscv64: Factor encode_vi_raw() out of encode_vi() tcg/riscv64: Use a uimm5 encoder for vector shift immediates tcg/riscv64: Extract elements for vector arithmetic immediates tcg/riscv64: Fix constant handling in vector comparisons and selects tcg/riscv64: Fix logical vector immediate matching and emission tests/tcg/aarch64: Add vector immediate regression tests tcg/riscv64/tcg-target-con-set.h | 1 + tcg/riscv64/tcg-target-con-str.h | 1 + tests/tcg/aarch64/sve-vec-imm.c | 233 +++++++++++++++++++++++++++++++ tcg/riscv64/tcg-target.c.inc | 116 ++++++++++++--- tests/tcg/aarch64/meson.build | 1 + 5 files changed, 330 insertions(+), 22 deletions(-) create mode 100644 tests/tcg/aarch64/sve-vec-imm.c -- 2.55.0
