On 2026-10-28 15:33, Philippe Mathieu-Daudé wrote: > Move the OPIVI field layout into encode_vi_raw(), keeping the > simm5 check in encode_vi(). The next commit adds a uimm5 variant > for the vector shift instructions. No functional change. > > Signed-off-by: Philippe Mathieu-Daudé <[email protected]> > --- > tcg/riscv64/tcg-target.c.inc | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/tcg/riscv64/tcg-target.c.inc b/tcg/riscv64/tcg-target.c.inc > index 03f32c5819f3..712170c1203e 100644 > --- a/tcg/riscv64/tcg-target.c.inc > +++ b/tcg/riscv64/tcg-target.c.inc > @@ -534,12 +534,18 @@ static tcg_insn_unit encode_j(RISCVInsn opc, TCGReg rd, > tcg_target_long imm) > > /* Type-OPIVI */ > > +static tcg_insn_unit encode_vi_raw(RISCVInsn opc, TCGReg rd, unsigned imm5, > + TCGReg vs2, bool vm) > +{ > + return opc | (rd & 0x1f) << 7 | (imm5 & 0x1f) << 15 | > + (vs2 & 0x1f) << 20 | (vm << 25); > +} > + > static tcg_insn_unit encode_vi(RISCVInsn opc, TCGReg rd, tcg_target_long imm, > TCGReg vs2, bool vm) > { > tcg_debug_assert(imm == sextract32(imm, 0, 5)); > - return opc | (rd & 0x1f) << 7 | (imm & 0x1f) << 15 | > - (vs2 & 0x1f) << 20 | (vm << 25); > + return encode_vi_raw(opc, rd, imm, vs2, vm); > } > > /* Type-OPIVV/OPMVV/OPIVX/OPMVX, Vector load and store */
Reviewed-by: Aurelien Jarno <[email protected]> -- Aurelien Jarno GPG: 4096R/1DDD8C9B [email protected] http://aurel32.net
