On 10/28/26 09:33, Philippe Mathieu-Daudé wrote:
RVV shift .vi forms take an unsigned 5-bit immediate, but encode_vi() checks for simm5, so shift counts 16..31 trip the debug assertion (and are undefined behaviour in release builds).Add encode_vi_u() and use it in tcg_out_vshifti(). Fixes: 006352d69f14 ("tcg/riscv64: Assert immediate in range ...") Signed-off-by: Philippe Mathieu-Daudé<[email protected]> --- tcg/riscv64/tcg-target.c.inc | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson <[email protected]> r~
