Atlantis includes a 32-bit RISC-V core (RCPU) used for boot, low-level control, and ongoing system management [1]. This series is the first step in adding the RCPU to the tt-atlantis machine. The RCPU shares access to most peripherals with the Ascalon cores. However, the RCPU has a different memory view. This requires a different memory map and a private memory container that the SoC aliases the shared devices into, at the addresses the RCPU expects.
On hardware, the RCPU is responsible for loading images from the boot medium into DRAM and releasing the Ascalon cores from reset, via the CPL. This functionality is not implemented in these changes. The images for the Ascalon cores continue to be loaded directly into DRAM via command line arguments and the Ascalon cores start executing at reset. With these changes, running tt-atlantis with rcpu=on will create a separate CPUCluster with the RCPU, giving gdb two inferiors. If no bootrom is provided, the RCPU hart will be held powered off. With a bootrom provided, via tt-atlantis,rcpu=on,bootrom=, the RCPU will execute the image and console output is on the second command line serial. This series does not provide a binary to test on the RCPU, it is in active development and not publicly available. The QEMU tests are updated to test booting of the Ascalon cores with and without the RCPU modeled. The machine properties related to the cpus, smp count and cpu-type, apply to the Ascalon cluster. The RCPU is an auxiliary core and is not configurable. See docs/system/riscv/tt_atlantis.rst for usage. [1] https://github.com/tenstorrent/atlantis-soc-docs/blob/main/data_sheet/atl_soc_data_sheet.pdf Changes from v2: - Add marchid for RCPU. Use it to check predicate for RCPU CSRs - Disable user_creatable for cluster devices. This really upset the review bots. - Use generic create_unimplemented_devices, squash "Back RCPU memory region by unimplemented device" into previous patch, it is only a single line change now. - Change default for rcpu to disabled to ensure no change to default smp behavior Changes from v1: - Include RCPU in smp cpu count - Fix incorrect address map naming of PRCM_DDR and DDR_CTRL - Drop valid_cpu_types enforcement Portia Stephens (9): hw/riscv/atlantis: Update fdt functions to take generic parameters hw/riscv/atlantis: Move Ascalon into cluster struct hw/riscv/atlantis: Store Ascalon memory in cluster struct hw/riscv/atlantis: Create CPU cluster for Atlantis cpus target/riscv: Add Tenstorrent Real-time CPU hw/riscv/atlantis: Add the RCPU to the Atlantis SoC hw/riscv/atlantis: Load the RCPU bootrom tests/functional/riscv64: Add rcpu to tt-atlantis tests docs/atlantis: Update Atlantis documentation to include the RCPU MAINTAINERS | 1 + docs/system/gdb.rst | 2 + docs/system/riscv/tt_atlantis.rst | 46 +- hw/riscv/Kconfig | 2 + hw/riscv/tt_atlantis.c | 635 +++++++++++++++---- include/hw/riscv/tt_atlantis.h | 76 ++- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 33 + target/riscv/tcg/csr.h | 3 + target/riscv/tcg/meson.build | 1 + target/riscv/tcg/tt_csr.c | 63 ++ tests/functional/riscv64/test_tt_atlantis.py | 10 +- 12 files changed, 743 insertions(+), 130 deletions(-) create mode 100644 target/riscv/tcg/tt_csr.c -- 2.43.0
