The RCPU is a high-performance 32-bit RISC-V embedded processor featuring a 6-stage, dual-issue superscalar pipeline, with tightly-coupled memories (TCMs), advanced interrupt controller (CLIC), and comprehensive debug/trace capabilities. It is designed for real-time, system management, and safety-critical applications requiring deterministic execution and low interrupt latency. See the Atlantis Datasheet, section 2.2 for more information [1].
The Atlantis SoC includes an RCPU used for boot, low-level control, and ongoing system management [1]. This adds a cpu entry for the RCPU and implementation specific CSRs. The CSRs are stubbed to allow code to run without exceptions but does not implement their functionality. [1] https://github.com/tenstorrent/atlantis-soc-docs/blob/main/data_sheet/atl_soc_data_sheet.pdf Signed-off-by: Portia Stephens <[email protected]> --- MAINTAINERS | 1 + target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 33 +++++++++++++++++++ target/riscv/tcg/csr.h | 3 ++ target/riscv/tcg/meson.build | 1 + target/riscv/tcg/tt_csr.c | 63 ++++++++++++++++++++++++++++++++++++ 6 files changed, 102 insertions(+) create mode 100644 target/riscv/tcg/tt_csr.c diff --git a/MAINTAINERS b/MAINTAINERS index 4ca1751e30..cfbb322da7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1850,6 +1850,7 @@ R: Portia Stephens <[email protected]> L: [email protected] S: Supported F: docs/system/riscv/tt_*.rst +F: target/riscv/tcg/tt_*.c F: hw/misc/tt_*.c F: hw/riscv/tt_*.c F: include/hw/misc/tt_*.h diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 61234842e3..72570ed47e 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -57,6 +57,7 @@ #define TYPE_RISCV_CPU_THEAD_C908V RISCV_CPU_TYPE_NAME("thead-c908v") #define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1") #define TYPE_RISCV_CPU_TT_ASCALON RISCV_CPU_TYPE_NAME("tt-ascalon") +#define TYPE_RISCV_CPU_TT_RCPU RISCV_CPU_TYPE_NAME("tt-rcpu") #define TYPE_RISCV_CPU_XIANGSHAN_NANHU RISCV_CPU_TYPE_NAME("xiangshan-nanhu") #define TYPE_RISCV_CPU_XIANGSHAN_KMH RISCV_CPU_TYPE_NAME("xiangshan-kunminghu") #define TYPE_RISCV_CPU_MIPS_P8700 RISCV_CPU_TYPE_NAME("mips-p8700") diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5a0529fbda..bcdac7c82f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -3480,6 +3480,39 @@ static const TypeInfo riscv_cpu_type_infos[] = { .cfg.pmp_regions = 8 ), +#if defined(TARGET_RISCV32) || \ + (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY)) + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_TT_RCPU, TYPE_RISCV_VENDOR_CPU, + .misa_mxl_max = MXL_RV32, + .misa_ext = RVI | RVM | RVA | RVB | RVC | RVD | RVF | RVU, + .priv_spec = PRIV_VERSION_1_13_0, + + .cfg.mmu = false, + .cfg.ext_zbc = true, + + .cfg.ext_zba = true, + .cfg.ext_zbb = true, + .cfg.ext_zbs = true, + .cfg.ext_zca = true, + .cfg.ext_zcb = true, + .cfg.ext_zifencei = true, + .cfg.ext_zicsr = true, + .cfg.ext_zicbom = true, + .cfg.ext_zicntr = true, + .cfg.ext_zihpm = true, + .cfg.ext_zicond = true, + .cfg.pmp = true, + /* + * marchid for the Atlantis RCPU. The RCPU is based off the Rondel CPU. + * Future Rondel cores may have a different marchid + */ + .cfg.marchid = 0x80000171, +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) + .custom_csrs = tt_csr_list, +#endif + ), +#endif + #if defined(TARGET_RISCV32) || \ (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY)) DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE32, TYPE_RISCV_DYNAMIC_CPU, diff --git a/target/riscv/tcg/csr.h b/target/riscv/tcg/csr.h index 53ba3b4a4d..4bc55b70d6 100644 --- a/target/riscv/tcg/csr.h +++ b/target/riscv/tcg/csr.h @@ -87,6 +87,9 @@ extern const RISCVCSR th_csr_list[]; /* Implemented in mips_csr.c */ extern const RISCVCSR mips_csr_list[]; +/* In tt_csr.c */ +extern const RISCVCSR tt_csr_list[]; + /* PMP CSRs, defined in pmp.c */ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, target_ulong val); diff --git a/target/riscv/tcg/meson.build b/target/riscv/tcg/meson.build index 86805b30cb..77357475c3 100644 --- a/target/riscv/tcg/meson.build +++ b/target/riscv/tcg/meson.build @@ -25,6 +25,7 @@ riscv_system_ss.add(files( 'pmp.c', 'pmu.c', 'th_csr.c', + 'tt_csr.c', )) diff --git a/target/riscv/tcg/tt_csr.c b/target/riscv/tcg/tt_csr.c new file mode 100644 index 0000000000..6ab9117486 --- /dev/null +++ b/target/riscv/tcg/tt_csr.c @@ -0,0 +1,63 @@ +/* + * Tenstorrent CPU implementation specifics. + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright 2026 Tenstorrent + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "target/riscv/tcg/csr.h" + +/* RCPU custom CSRs */ +#define RCPU_CSR_MICACHE 0x7c0 +#define RCPU_CSR_MDCACHE 0x7c1 +#define RCPU_CSR_MITCMCR 0x7c5 +#define RCPU_CSR_MDTCMCR 0x7c6 +#define RCPU_CSR_MHCR 0x7c7 +#define RCPU_CSR_MEXINFO 0x7ca +#define RCPU_CSR_MNMIE 0xbc6 + +#define RCPU_MARCH_ID 0x80000171 + +/* predicate for an RCPU core */ +static RISCVException rcpu(CPURISCVState *env, int csrno) +{ + if (env_archcpu(env)->cfg.marchid != RCPU_MARCH_ID) { + return RISCV_EXCP_ILLEGAL_INST; + } + return RISCV_EXCP_NONE; +} + +static RISCVException read_zero(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = 0; + + return RISCV_EXCP_NONE; +} + +static RISCVException write_none(CPURISCVState *env, int csrno, + target_ulong val, uintptr_t ra) +{ + return RISCV_EXCP_NONE; +} + +const RISCVCSR tt_csr_list[] = { + { .csrno = RCPU_CSR_MICACHE, + .csr_ops = { "micache", rcpu, read_zero, write_none} }, + { .csrno = RCPU_CSR_MDCACHE, + .csr_ops = { "mdcache", rcpu, read_zero, write_none} }, + { .csrno = RCPU_CSR_MITCMCR, + .csr_ops = { "mitcmcr", rcpu, read_zero, write_none} }, + { .csrno = RCPU_CSR_MDTCMCR, + .csr_ops = { "mdtcmcr", rcpu, read_zero, write_none} }, + { .csrno = RCPU_CSR_MHCR, + .csr_ops = { "mhcr", rcpu, read_zero, write_none} }, + { .csrno = RCPU_CSR_MEXINFO, + .csr_ops = { "mexinfo", rcpu, read_zero, write_none} }, + { .csrno = RCPU_CSR_MNMIE, + .csr_ops = { "mnmie", rcpu, read_zero, write_none} }, + { }, +}; -- 2.43.0
