On Mon, 2013-08-12 at 10:52 +0100, Peter Maydell wrote: > On 12 August 2013 10:50, Benjamin Herrenschmidt > <b...@kernel.crashing.org> wrote: > > I must be confused ... you mentioned in a previous discussion around > > endianness that on some ARM cores at least, when changing the OS > > endianness, you had to configure a different lane swapping in the bridge > > to the the IO devices (AXI ?) > > No, that's just the implementation -- the bit in the control > register is effectively controlling whether there is byte lane > swapping in the part of the CPU which is the data path between > it and its bus to the outside world.
I find it amazing that an OS can touch that without hitting the hypervisor :-) Anyway, ok, we do need to poll from virtio then, but we probably need to cache as well, no ? When do you sample it in qemu ? Cheers, Ben.
