On 12 August 2013 10:56, Benjamin Herrenschmidt <b...@kernel.crashing.org> wrote: > On Mon, 2013-08-12 at 10:52 +0100, Peter Maydell wrote: >> On 12 August 2013 10:50, Benjamin Herrenschmidt >> <b...@kernel.crashing.org> wrote: >> > I must be confused ... you mentioned in a previous discussion around >> > endianness that on some ARM cores at least, when changing the OS >> > endianness, you had to configure a different lane swapping in the bridge >> > to the the IO devices (AXI ?) >> >> No, that's just the implementation -- the bit in the control >> register is effectively controlling whether there is byte lane >> swapping in the part of the CPU which is the data path between >> it and its bus to the outside world. > > I find it amazing that an OS can touch that without hitting the > hypervisor :-)
It's no different to having a userspace process able to have a different setting from the OS, really. (There is an equivalent bit in another register that controls what endianness we use if we trap to hyp mode.) > Anyway, ok, we do need to poll from virtio then, but we > probably need to cache as well, no ? > > When do you sample it in qemu ? It's a bit theoretical at the moment since QEMU's ARM code kind of assumes little endian. I would expect that at the point when virtio was in an MMIO callback the CPUState struct would have been updated via the usual sync process in kvm_arch_get_registers(). -- PMM
