On Fri, May 16, 2014 at 03:19:36PM +0100, Peter Maydell wrote: > On 8 May 2014 01:13, Edgar E. Iglesias <edgar.igles...@gmail.com> wrote: > > On Wed, May 07, 2014 at 03:10:54PM +1000, Peter Crosthwaite wrote: > >> On Tue, May 6, 2014 at 4:08 PM, Edgar E. Iglesias > >> <edgar.igles...@gmail.com> wrote: > >> > From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> > >> > > >> > No functional change. > >> > Prepares for future additions of the EL2 and 3 versions of this reg. > >> > > >> > Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> > >> > --- > >> > target-arm/cpu.h | 3 ++- > >> > target-arm/helper-a64.c | 4 ++-- > >> > target-arm/helper.c | 3 ++- > >> > target-arm/kvm64.c | 4 ++-- > >> > target-arm/machine.c | 2 +- > >> > target-arm/op_helper.c | 6 +++--- > >> > 6 files changed, 12 insertions(+), 10 deletions(-) > >> > > >> > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > >> > index c83f249..eb7a0f5 100644 > >> > --- a/target-arm/cpu.h > >> > +++ b/target-arm/cpu.h > >> > @@ -162,7 +162,8 @@ typedef struct CPUARMState { > >> > uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ > >> > uint64_t daif; /* exception masks, in the bits they are in in > >> > PSTATE */ > >> > > >> > - uint64_t elr_el1; /* AArch64 ELR_EL1 */ > >> > +#define ELR_EL_IDX(x) (x - 1) > >> > + uint64_t elr_el[1]; /* AArch64 exception link regs */ > >> > >> Is it perhaps just easier to waste the space and always pad these > >> EL-banked CP arrays out to length 4 you can just use literal numbers > >> in the code? Probably make life easier when introspecting the CPU > >> state in GDB too. > > > > Thanks Peter, > > > > I've fixed all your comments except this one. I considered this > > pattern but avoided it due to the bloating of CPUARMState. Anyway, > > I'm happy to change to this full array allocation if others agree. > > > > PMM, what is your preference on this? > > I think I'd rather we just padded the array to length 4.
Sounds good, I'll change the pattern. Cheers, Edgar