Hi Pranith, On 10/01/2015 11:34 AM, Pranith Kumar wrote: > Hi Christoph, > > On the qemu mailing list you mentioned that you use perf events in > linux ARM64 guests. I was wondering how you enabled access to the PMU? > > I get illegal instruction whenever I execute any "MSR PMUSERENR_EL0, > 1" to enable user access. Any help is appreciated.
Are you using KVM or TCG (are you running on an x86 host or an arm64 host)? We have published some patches implementing the PMU registers and instruction counting (but not any other events) for TCG mode [1], but more work is required to get these changes into shape for inclusion upstream. 1. https://lists.nongnu.org/archive/html/qemu-devel/2015-08/msg00567.html To guide and justify the changes I'm currently trying to write kvm-unit-tests that measure A) IPC using PMCCNTR_EL0 (implemented upstream, at least when not using -icount) and code with known length in instructions; B) CPU frequency using PMCCNTR_EL0 and CNTVCT_EL0; and C) instructions event in the PMU for code with known length in instructions If you're using KVM, I think Shannon Zhao at Linaro has been working on that. Christopher Covington -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
