On 10/01/2015 03:32 PM, Pranith Kumar wrote: > On Thu, Oct 1, 2015 at 12:21 PM, Christopher Covington > <c...@codeaurora.org> wrote: >> >> Are you using KVM or TCG (are you running on an x86 host or an arm64 host)? > > I am using TCG, aarch64-softmmu on x86 host. > >> >> We have published some patches implementing the PMU registers and instruction >> counting (but not any other events) for TCG mode [1], but more work is >> required to get these changes into shape for inclusion upstream. >> >> 1. https://lists.nongnu.org/archive/html/qemu-devel/2015-08/msg00567.html > > Thanks for the pointer. From the patch series I can see that patches 7 > and 9 are for enabling PMU in ARM virt. Do you plan on submitting > them upstream? > I will try these patches locally and see how it goes. > >> To guide and justify the changes I'm currently trying to write kvm-unit-tests >> that measure >> >> A) IPC using PMCCNTR_EL0 (implemented upstream, at least when not using >> -icount) and code with known length in instructions; > > PMCCNTR_EL0 always returns 0 for me(in 2.4, will check tip).
Make sure it's enabled (PMCR_EL0 = 1). I meant to copy you on the patch but forgot. Please see "[kvm-unit-tests PATCHv2] arm: Add PMU test" for an example. >> B) CPU frequency using PMCCNTR_EL0 and CNTVCT_EL0; and >> C) instructions event in the PMU for code with known length in instructions > > I am guessing these two are not upstream yet, would be great to see it there. PMCCNTR_EL0 and CNTVCT_EL0 are supported upstream (so B should work). Regular events, such as the instructions event (8 IIRC), are not yet supported (further changes are required before C will work). Christopher Covington -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
