On Thu, Oct 1, 2015 at 12:21 PM, Christopher Covington <c...@codeaurora.org> wrote: > > Are you using KVM or TCG (are you running on an x86 host or an arm64 host)?
I am using TCG, aarch64-softmmu on x86 host. > > We have published some patches implementing the PMU registers and instruction > counting (but not any other events) for TCG mode [1], but more work is > required to get these changes into shape for inclusion upstream. > > 1. https://lists.nongnu.org/archive/html/qemu-devel/2015-08/msg00567.html Thanks for the pointer. From the patch series I can see that patches 7 and 9 are for enabling PMU in ARM virt. Do you plan on submitting them upstream? I will try these patches locally and see how it goes. > > To guide and justify the changes I'm currently trying to write kvm-unit-tests > that measure > > A) IPC using PMCCNTR_EL0 (implemented upstream, at least when not using > -icount) and code with known length in instructions; PMCCNTR_EL0 always returns 0 for me(in 2.4, will check tip). > B) CPU frequency using PMCCNTR_EL0 and CNTVCT_EL0; and > C) instructions event in the PMU for code with known length in instructions I am guessing these two are not upstream yet, would be great to see it there. Thanks! -- Pranith
