On Wed, Apr 25, 2018 at 5:00 PM Michael Clark <m...@sifive.com> wrote:
> Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> > Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> > Cc: Palmer Dabbelt <pal...@sifive.com> > Cc: Alistair Francis <alistair.fran...@wdc.com> > Signed-off-by: Michael Clark <m...@sifive.com> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Alistair > --- > target/riscv/translate.c | 1 - > 1 file changed, 1 deletion(-) > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 808eab7..c3a029a 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -280,7 +280,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1, > tcg_gen_andi_tl(source2, source2, 0x1F); > tcg_gen_sar_tl(source1, source1, source2); > break; > - /* fall through to SRA */ > #endif > case OPC_RISC_SRA: > tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1); > -- > 2.7.0
