From: Yongbok Kim <yongbok....@mips.com>
Add emulation of misc nanoMIPS instructions situated in pool32axf.
Signed-off-by: Yongbok Kim <yongbok....@mips.com>
Signed-off-by: Aleksandar Markovic <amarko...@wavecomp.com>
Signed-off-by: Stefan Markovic <smarko...@wavecomp.com>
---
target/mips/translate.c | 94 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 94 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 488bed9..6c68a1f 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16627,6 +16627,93 @@ static void gen_pool32a0_nanomips_insn(DisasContext
*ctx)
}
}
+static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
+{
+ int rt = (ctx->opcode >> 21) & 0x1f;
+ int rs = (ctx->opcode >> 16) & 0x1f;
+
+ switch ((ctx->opcode >> 6) & 0x07) {
+ case NM_POOL32AXF_4:
+ case NM_POOL32AXF_5:
+ switch ((ctx->opcode >> 9) & 0x7f) {
+ case NM_CLO:
+ gen_cl(ctx, OPC_CLO, rt, rs);
+ break;
+ case NM_CLZ:
+ gen_cl(ctx, OPC_CLZ, rt, rs);
+ break;
+#ifndef CONFIG_USER_ONLY
+ case NM_TLBP:
+ gen_cp0(env, ctx, OPC_TLBP, 0, 0);
+ break;
+ case NM_TLBR:
+ gen_cp0(env, ctx, OPC_TLBR, 0, 0);
+ break;
+ case NM_TLBWI:
+ gen_cp0(env, ctx, OPC_TLBWI, 0, 0);
+ break;
+ case NM_TLBWR:
+ gen_cp0(env, ctx, OPC_TLBWR, 0, 0);
+ break;
+ case NM_TLBINV:
+ gen_cp0(env, ctx, OPC_TLBINV, 0, 0);
+ break;
+ case NM_TLBINVF:
+ gen_cp0(env, ctx, OPC_TLBINVF, 0, 0);
+ break;
+ case NM_DI:
+ check_cp0_enabled(ctx);
+ {
+ TCGv t0 = tcg_temp_new();
+
+ save_cpu_state(ctx, 1);
+ gen_helper_di(t0, cpu_env);
+ gen_store_gpr(t0, rt);
+ /* Stop translation as we may have switched the execution mode */
+ ctx->base.is_jmp = DISAS_STOP;
+ tcg_temp_free(t0);
+ }
+ break;
+ case NM_EI:
+ check_cp0_enabled(ctx);
+ {
+ TCGv t0 = tcg_temp_new();
+
+ save_cpu_state(ctx, 1);
+ gen_helper_ei(t0, cpu_env);
+ gen_store_gpr(t0, rt);
+ /* Stop translation as we may have switched the execution mode */
+ ctx->base.is_jmp = DISAS_STOP;
+ tcg_temp_free(t0);
+ }
+ break;
+ case NM_RDPGPR:
+ gen_load_srsgpr(rs, rt);
+ break;
+ case NM_WRPGPR:
+ gen_store_srsgpr(rs, rt);
+ break;
+ case NM_WAIT:
+ gen_cp0(env, ctx, OPC_WAIT, 0, 0);
+ break;
+ case NM_DERET:
+ gen_cp0(env, ctx, OPC_DERET, 0, 0);
+ break;
+ case NM_ERETX:
+ gen_cp0(env, ctx, OPC_ERET, 0, 0);
+ break;
+#endif
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+}
+
static void gen_pool32f_nanomips_insn(DisasContext *ctx)
{
int rt, rs, rd;
@@ -16996,6 +17083,13 @@ static int decode_nanomips_32_48_opc(CPUMIPSState
*env, DisasContext *ctx)
gen_pool32a0_nanomips_insn(ctx);
break;
case NM_POOL32A7:
+ {
+ switch ((ctx->opcode >> 3) & 0x07) {
+ case NM_POOL32AXF:
+ gen_pool32axf_nanomips_insn(env, ctx);
+ break;
+ }
+ }
break;
default:
generate_exception_end(ctx, EXCP_RI);
--
2.7.4
