> Subject: [PATCH v2 01/33] target/mips: Add nanoMIPS OPCODE table
>
> From: Yongbok Kim <yongbok....@mips.com>
>
> nanoMIPS opcodes are organized by so-called instruction pools.
>
> Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
> Signed-off-by: Yongbok Kim <yongbok....@mips.com>
> Signed-off-by: Aleksandar Markovic <amarko...@wavecomp.com>
> Signed-off-by: Stefan Markovic <smarko...@wavecomp.com>
> ---
> target/mips/mips-defs.h | 4 +
> target/mips/translate.c | 674
> ++++++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 678 insertions(+)
>
I think changes in target/mips/mips-defs.h shoudl be in a separate patch.
For opcodes, a comment explaining instruction pool organization would be
helpful.
Also, there is no distinction between opcode constants for instruction and
instuction pools: they all begin NM_ plus instruction/pool mnemonic. If there
is enough time, that should be corrected so that trere are NM_IN_XXX and
NM_PL_YYY opcodes, let's say.
> diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
> index d239069..eadc1d8 100644
> --- a/target/mips/mips-defs.h
> +++ b/target/mips/mips-defs.h
> @@ -39,6 +39,7 @@
> #define ISA_MIPS64R5 0x00001000
> #define ISA_MIPS32R6 0x00002000
> #define ISA_MIPS64R6 0x00004000
> +#define ISA_NANOMIPS32 0x00008000
>
> /* MIPS ASEs. */
> #define ASE_MIPS16 0x00010000
> @@ -87,6 +88,9 @@
> #define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6)
> #define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6)
>
> +/* MIPS Technologies "nanoMIPS" */
> +#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32)
> +
> /* Strictly follow the architecture standard:
> - Disallow "special" instruction handling for PMON/SPIM.
> Note that we still maintain Count/Compare to match the host clock. */
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index de0d55b..3ccf6fc 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -15644,6 +15644,680 @@ static int decode_micromips_opc (CPUMIPSState *env,
> DisasContext > *ctx)
> return 2;
> }
>
> +/*
> + *
> + * nanoMIPS opcodes
> + *
> + */
> +
> +/* MAJOR, P16, and P32 pools opcodes */
> +enum {
> + NM_P_ADDIU = 0x00,
> + NM_ADDIUPC = 0x01,
> + NM_MOVE_BALC = 0x02,
