On Sun, Mar 6, 2011 at 6:47 PM, Blue Swirl <blauwir...@gmail.com> wrote:
> On Sun, Mar 6, 2011 at 6:31 PM, Anthony Liguori <anth...@codemonkey.ws> wrote:
>> On 02/13/2011 03:10 PM, Blue Swirl wrote:
>>>
>>> Convert to qdev. Don't expose PITState.
>>>
>>> Signed-off-by: Blue Swirl<blauwir...@gmail.com>
>>> ---
>>> hw/i8254.c | 61
>>> +++++++++++++++++++++++++++++++++++++--------------
>>> hw/mips_fulong2e.c | 4 +-
>>> hw/mips_jazz.c | 4 +-
>>> hw/mips_malta.c | 4 +-
>>> hw/mips_r4k.c | 4 +-
>>> hw/pc.c | 5 +--
>>> hw/pc.h | 25 ++++++++++++++------
>>> hw/pcspk.c | 4 +-
>>> hw/ppc_prep.c | 4 +-
>>> 9 files changed, 75 insertions(+), 40 deletions(-)
>>>
>>> diff --git a/hw/i8254.c b/hw/i8254.c
>>> index 06b225c..680caab 100644
>>> --- a/hw/i8254.c
>>> +++ b/hw/i8254.c
>>> @@ -53,9 +53,12 @@ typedef struct PITChannelState {
>>> qemu_irq irq;
>>> } PITChannelState;
>>>
>>> -struct PITState {
>>> +typedef struct PITState {
>>> + ISADevice dev;
>>>
>>
>> The PIT is not an ISA device. Modelling it as such is worse than leaving it
>> unmodelled.
>
> No. These days, PIT is part of Super I/O chip, which is accessed via
> LPC bus. LPC is from software point of view equal to ISA. Therefore,
> in absence of LPC, ISA is correct.
Actually, I could not find any pure Super I/O chips (without south
bridge functionality) which also contained PIT and other legacy
devices, instead most south bridges (with or without a Super I/O)
implement these. Then PIT could be a SysBusDevice, though SysBus does
not know anything about I/O ports. I think ISADevice is not totally
wrong.
