On Mon, Jun 24, 2019 at 12:05:07PM +0100, Dave Martin wrote: > On Fri, Jun 21, 2019 at 05:34:13PM +0100, Andrew Jones wrote: > > The purpose of this check should probably at least be described in a > comment -- i.e., what actually depends on this?
I was thinking the already present "Bits other than [3:0] are RAZ/WI." explained that, but how about this for an improvement? /* * Only the lowest 4 bits of ZCR_ELx may be used to constrain the vector * length, the rest of the bits are RAZ/WI. Since the vector length of * 128-bits (1 in quadwords) is represented as zero in ZCR_ELx, and all * vector lengths are represented as their length in quadwords minus 1, * then four bits allow up to quadword 16 to be selected. */ Thanks, drew > > Cheers > ---Dave > > > Suggested-by: Dave Martin <dave.mar...@arm.com> > > Signed-off-by: Andrew Jones <drjo...@redhat.com> > > --- > > target/arm/helper.c | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/target/arm/helper.c b/target/arm/helper.c > > index df4276f5f6ca..edba94004e0b 100644 > > --- a/target/arm/helper.c > > +++ b/target/arm/helper.c > > @@ -5319,6 +5319,7 @@ static void zcr_write(CPUARMState *env, const > > ARMCPRegInfo *ri, > > int new_len; > > > > /* Bits other than [3:0] are RAZ/WI. */ > > + QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16); > > raw_write(env, ri, value & 0xf); > > > > /* > > -- > > 2.20.1 > > >